Abstract

As scale down the standard single-gate bulk MOSFET dimensions, vast challenges in the nanometer regime due to the brutal short-channel effects arises that grounds an exponential increases in the leakage current, power consumption and enriched the sensitivity in process variations. Double gate and multi-gate technology alleviate these restrictions by producing a stronger control over a thin silicon body with electrically coupled gates. In this paper, proposed a methodology for independent gate (IG) FinFET Nand circuit in which applies multiple supplies for controlling the threshold voltage V_thby which IG FinFET can improve the speed, saving the power and minimize the area of the circuit by 23-25%. The most advantageous IG keeper gate bias conditions are identified for reaching maximum savings (approx 40-43%) in delay and power (24-28%) while maintaining identical noise immunity as compared to the simple supply IG-FinFET domino circuits. Here the circuit efficiency also enhances.

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