Research Article
FPGA-based New Hybrid Adder Design with the Optimal Bit-Width Configuration
|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 65 - Issue 11 |
| Published: March 2013 |
| Authors: Mahmoud A. M. Alshewimy, Ahmet Sertbas |
10.5120/10968-6100
|
Mahmoud A. M. Alshewimy, Ahmet Sertbas . FPGA-based New Hybrid Adder Design with the Optimal Bit-Width Configuration. International Journal of Computer Applications. 65, 11 (March 2013), 15-19. DOI=10.5120/10968-6100
@article{ 10.5120/10968-6100,
author = { Mahmoud A. M. Alshewimy,Ahmet Sertbas },
title = { FPGA-based New Hybrid Adder Design with the Optimal Bit-Width Configuration },
journal = { International Journal of Computer Applications },
year = { 2013 },
volume = { 65 },
number = { 11 },
pages = { 15-19 },
doi = { 10.5120/10968-6100 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2013
%A Mahmoud A. M. Alshewimy
%A Ahmet Sertbas
%T FPGA-based New Hybrid Adder Design with the Optimal Bit-Width Configuration%T
%J International Journal of Computer Applications
%V 65
%N 11
%P 15-19
%R 10.5120/10968-6100
%I Foundation of Computer Science (FCS), NY, USA
Abstract
This paper presents FPGA-based design of hybrid adder with the optimal bit-width configuration(out of alarge number of possible configurations) of each of the sub-adders constitute the proposed hybrid adder using a high level automated methodology. Algebraicoptimization model for the hybrid adderis built to produce the best choice of types and bit-widths of the sub-adders. In context of this work, several classes of parallel adders are designed and its performance is evaluated to serve as sub-adders inside the hybrid adder. The results show that the proposed model gains a high flexibility in allowing design tradeoffs between the performance criteria delay and areaand successfully to generate the optimalbit-width configurations of the hybrid adder.
References
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