Research Article
An Efficient Design of 3bit and 4bit Flash ADC
|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 61 - Issue 11 |
| Published: January 2013 |
| Authors: Arunkumar P Chavan, Rekha G, P Narashimaraja |
10.5120/9974-4802
|
Arunkumar P Chavan, Rekha G, P Narashimaraja . An Efficient Design of 3bit and 4bit Flash ADC. International Journal of Computer Applications. 61, 11 (January 2013), 32-37. DOI=10.5120/9974-4802
@article{ 10.5120/9974-4802,
author = { Arunkumar P Chavan,Rekha G,P Narashimaraja },
title = { An Efficient Design of 3bit and 4bit Flash ADC },
journal = { International Journal of Computer Applications },
year = { 2013 },
volume = { 61 },
number = { 11 },
pages = { 32-37 },
doi = { 10.5120/9974-4802 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2013
%A Arunkumar P Chavan
%A Rekha G
%A P Narashimaraja
%T An Efficient Design of 3bit and 4bit Flash ADC%T
%J International Journal of Computer Applications
%V 61
%N 11
%P 32-37
%R 10.5120/9974-4802
%I Foundation of Computer Science (FCS), NY, USA
Abstract
The performance of Flash Analog-to-Digital converter is greatly influenced by the choice of Comparator and Thermometer-to- Binary encoder design. The work describes the design and pre-simulation of a , 3bit and an 4bit analog to digital converter for low power CMOS. It requires 2N-1 comparators, an encoder to convert thermometer code to binary code. The design is simulated in cadence environment using spectre simulator under 90nm technology. The pre simulation results for the design shows a low power dissipation of 87uw for the comparator and 1. 05mW and 1. 984mW power dissipation for 3-bit and 4-bit Flash ADC respectively. The circuit operates with an input frequency of 25MHz and 1. 5V supply with a conversion time of 2. 162ns and 6. 182ns for 3-bit and 4-bit ADC respectively.
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