Abstract

In the present time, improvement of some fields like nanotechnology, low power design and quantum computing reversible logic circuit has emerged as a great prospect of research. With the help of using existing reversible gates a 4 bit reversible comparator based on classical logic circuit is represented. This work presents a BIST based architecture of a comparator design has a reduced number of constant inputs, garbage outputs and quantum cost.

References

• Himanshu Thapliyal, Nagarajan Ranganathan and Ryan Ferreira, “Design of a Comparator Tree Based on Reversible Logic”, IEEE international conference, pp.1113-1116, Aug 2010.
• Rakshith Saligram and Rakshith T. R., “Design of Low Logical Cost Adders using Novel Parity Confirming Toffili Gate”, IEEE International Conference on Emerging Trends in Communication, Control, Signal Processing and Computing Applications,pp-46-51, 2013.
• V. Kirthi and G. Mamatha Samson, “Design of BIST with Low Power Test Pattern Generator”, IOSR Journal of VLSI and Signal Processing, Vol.4 No.5, pp.30-39, Sept.-Oct. 2014.
• M. Saravanan and K. Suresh Manic, “Energy Efficient Code Converters using Reversible Logic Gates”, International Conference on Green Perfermance Computing, pp-14-15, March 2013.
• Neeraj Kumar Misra, Mukesh Kumar Kushwaha and Subodh Wairya, “Cost Efficient Design of Reversible Adder Circuits for Low POwer Applications”, International Journal of Computer Applications, Vol-117 No-9, pp-37-45, May 2015.
• Bahram Dehghan, Abdolreza and Jafar Zare, “Design of Low Power Comparator using DG Gate”, Scientific Research Circuits and Systems, Vol-7 No-12, pp-7-12, 2014.
• Harpreet Singh and Chakshu Goel, “Design of a Power Efficient Reversible Adder-Subtractor”, International Journal of Advanced Research in Computer Engineering and Technology, Vol-4 No-4, pp-1305-1308, April 2015.
• Dibal P.Y., “Design of a 4-bit Magnitude Comparator using Simulink”, Arid Zone Journal of Engineering, Technology and Environment, Vol-9 No-16, pp-9-16, August 2013.
• Shivanappa Mantur, Chidanand Murthy M. V., M. Z. Kurian and H.S. Guruprasad, “Design of 4x4 Reversible Square Quantum Circuitry”, International Journal of Emerging Technology in Computer Science and Electronics, Vol-14 No-2, pp-886-890, April 2015.
• Diganta Sengupta, Mahamuda Sultana and Atal Chaudhuri, “Realization of a Novel Reversible SCG Gate and its Application for Designing Parallel Adder-Subtractor and Matched Logic”, International Journal of Computer Applications, Vol-31 No-9, pp-30-35, October 2011.
• Sravanth and T. Venkata Lakshmi, “VLSI Implementation of ALU using Reversible Logic with Vedic Mathematics”, International Journal of Scientific Engineering and Technology Research, Vol-4, No-1, pp-142-146, January 2015.
• Ali Newaz Bahar, Sajjad Waheed and Nazir Hossain, “A New Approach of Presenting Reversible Logic Gate in Nanoscale”, SpringerPlus Open Journal, 2015.
• A. Kavitha, G. Seetharaman, T. N. Prabakar and Shrinithi S., “Design of low power TPG using LP-LFSR”, IEEE Third International Conference on Intelligent Systems Modelling and Simulation, pp-334-338, 2012.
• Shikha Kakar, Balvinder Singh and Arun Khosla, “Implementation of BIST Capability using LFSR Techniques in UART”, International Journal of Recent Trends in Engineering, Vol-1, No-3, pp-301-304, May 2009.
• Kavya Shree C., Praveen Kumar Y. G. and M. Z. Kurian, “A Novel approach for Implementation of LFSR using Reversible Logic”, International Journal of Recent Advances in Engineering and Technology, Vol-3 No-4, pp-9-12, 2015.
• Soolmaz Abbasalizadeh, Behjat Forouzandeh and Hossein Aghababa, “4 Bit Comparator Design Based on Reversible Logic Gate”, Lecture Notes on Information Technology, Vol.1, No.3, pp.86-88, September 2013.
• Majid Haghparast, Leila, Rezazadeh and Vahedeh Seivani, “Design and Optimization of Nanometric Reversible 4 Bit Numerical Comparator”, Middle-East Journal of Scientific Research, vol.7, No.4, pp.581-584, Nov 2011.