Research Article
Comparative Analysis of Universal Gates using MCML and CMOS Technique
|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 118 - Issue 5 |
| Published: May 2015 |
| Authors: Ginni Jain, Keerti Vyas, Vijendra K Maurya, Rajeev Mathur |
10.5120/20743-3128
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Ginni Jain, Keerti Vyas, Vijendra K Maurya, Rajeev Mathur . Comparative Analysis of Universal Gates using MCML and CMOS Technique. International Journal of Computer Applications. 118, 5 (May 2015), 27-29. DOI=10.5120/20743-3128
@article{ 10.5120/20743-3128,
author = { Ginni Jain,Keerti Vyas,Vijendra K Maurya,Rajeev Mathur },
title = { Comparative Analysis of Universal Gates using MCML and CMOS Technique },
journal = { International Journal of Computer Applications },
year = { 2015 },
volume = { 118 },
number = { 5 },
pages = { 27-29 },
doi = { 10.5120/20743-3128 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2015
%A Ginni Jain
%A Keerti Vyas
%A Vijendra K Maurya
%A Rajeev Mathur
%T Comparative Analysis of Universal Gates using MCML and CMOS Technique%T
%J International Journal of Computer Applications
%V 118
%N 5
%P 27-29
%R 10.5120/20743-3128
%I Foundation of Computer Science (FCS), NY, USA
Abstract
MOS current mode logic (MCML) is an emerging logic family which is gaining attention due to its high speed of operation, robust performance and presence of mere switching noise as compared to the CMOS logic family. In this paper we have compared universal gates using MCML and conventional CMOS in terms of power and propagation delay at 16-nm Technology node. Comparative analysis shows that MCML universal gates has less power and delay as compared to conventional CMOS based universal gates at 16 nm technology. Variability analysis establishes MCML based universal gates as the most resilient and immune to various electrical parameters.
References
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