Research Article
Power and Area Efficient FLASH ADC Design using 65nm CMOS Technology
|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 97 - Issue 23 |
| Published: July 2014 |
| Authors: M. Abhilash Kumar, Ajay Kumar Dadoria, Kavita Khare |
10.5120/17319-7431
|
M. Abhilash Kumar, Ajay Kumar Dadoria, Kavita Khare . Power and Area Efficient FLASH ADC Design using 65nm CMOS Technology. International Journal of Computer Applications. 97, 23 (July 2014), 1-8. DOI=10.5120/17319-7431
@article{ 10.5120/17319-7431,
author = { M. Abhilash Kumar,Ajay Kumar Dadoria,Kavita Khare },
title = { Power and Area Efficient FLASH ADC Design using 65nm CMOS Technology },
journal = { International Journal of Computer Applications },
year = { 2014 },
volume = { 97 },
number = { 23 },
pages = { 1-8 },
doi = { 10.5120/17319-7431 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2014
%A M. Abhilash Kumar
%A Ajay Kumar Dadoria
%A Kavita Khare
%T Power and Area Efficient FLASH ADC Design using 65nm CMOS Technology%T
%J International Journal of Computer Applications
%V 97
%N 23
%P 1-8
%R 10.5120/17319-7431
%I Foundation of Computer Science (FCS), NY, USA
Abstract
This paper presents a design of a high speed Comparator design using 65nm digital CMOS technology on Cadence Virtuoso Design Tool. The proposed FLASH ADC Design consists of fully differential topology. The first stage provides a Voltage Divider circuit and the second stage is Comparator Design having high sampling frequency tolerance, and the high efficient common drain circuit provides high driving capability with relatively low power dissipation. It is used in more application for bandwidth and power and a high resolution is available for analog-to-digital converters (ADCs). Under 1 V supply voltage, the simulation results show that the proposed FLASH ADC Design is having a differential topology along with latching circuit.
References
- J. Ceballos, I. Galton, and G. Temes, "Stochastic analog-to digital conversion," in Proc. 48th Midwest Symp. Circuits and Systems, Aug. 2005, pp. 855 858.
- "Analog MOS Integrated circuits for Signal Processing", by Roubik Greegorian,Gabor C. TEMES.
- Amalan Nag, K. L. Baishnab F. A. Talukdar, Member, IEEE "Low Power, High Precision and Reduced Size CMOS Comparator for High Speed ADC Design" 2010 5th International Conference on Industrial and Information Systems, ICIIS 2010, Jul 29 - Aug 01, 2010, India.
- T. Sundsröm and A. Alvandpour, "Utilizing Process variations for reference generation in a flash ADC," IEEE Trans. Circuits Syst. II,vol. 56, pp. 364–368,May 2009.
- "Design of Analog CMOS Integrated Circuits", by Behzad Razavi, Tata McGraw Hill Edition 2002, ISBN – 0- 07-238032-2.
- K. N. Leung, P. K. T. Mok, "Analysis of Multistage amplifier frequency compensation", IEEE Trans. Circuits Systems I: Fund. Theory 48 (9) (2001) 1041- 1056.
- B. K. Ahuja, "An improved frequency compensation technique for CMOS operational amplifiers", IEEE J. Solid- State Circuits 18 (1983) 629–633.
- K. Kattmann and J. Barrow, "A technique for reducing differential non-linearity errors in flash A/D converters",in Proc. IEEE Int. Solid-State Circuits Conf. 1991, pp. 170–171.
- P. C. S. Scholtens and M. Vertregt,"A 6-b 1. 6 Gsamples/s flash ADC in 0. 18um CMOS using averaging termination,"IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1599-1609, Mar. 2002.
- Hank Zumbahlen, Basic Linear Design, Analog Devices, 2006, ISBN: 0-915550-28-1. Also available as Linear Circuit Design Handbook, Elsevier-Newnes, 2008, ISBN-10: 0750687037,ISBN-13: 978-0750687034. Chapter1.
- Walter G. Jung, Op Amp Applications, Analog Devices, 2002, ISBN 0-916550-26-5, Also available as Op Amp Applications Handbook, Elsevier/Newnes, 2005, ISBN 0-7506-7844-5. Chapter 1.
- INL and DNL definitions "A DNL error specification of less than or equal to 1LSB guarantees a monotonic transfer function with no missing codes. http://www. maxim-ic. com/app-notes/index. mvp/id/283.
- Erik Sail, Mark Vesterbacka , "A multiplexer based decoder for flash analog-to-digital converters," TENCON 2004. IEEE Region 10 Conference , 21-24 Nov. 2004, vol. 4, pp. 250- 253.
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