Research Article
Implementation of Multi Level Logic for Digital System
|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 97 - Issue 20 |
| Published: July 2014 |
| Authors: Prajyant Pathak, Braj Bihari Soni, Puran Gour |
10.5120/17124-7729
|
Prajyant Pathak, Braj Bihari Soni, Puran Gour . Implementation of Multi Level Logic for Digital System. International Journal of Computer Applications. 97, 20 (July 2014), 20-23. DOI=10.5120/17124-7729
@article{ 10.5120/17124-7729,
author = { Prajyant Pathak,Braj Bihari Soni,Puran Gour },
title = { Implementation of Multi Level Logic for Digital System },
journal = { International Journal of Computer Applications },
year = { 2014 },
volume = { 97 },
number = { 20 },
pages = { 20-23 },
doi = { 10.5120/17124-7729 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2014
%A Prajyant Pathak
%A Braj Bihari Soni
%A Puran Gour
%T Implementation of Multi Level Logic for Digital System%T
%J International Journal of Computer Applications
%V 97
%N 20
%P 20-23
%R 10.5120/17124-7729
%I Foundation of Computer Science (FCS), NY, USA
Abstract
A Multi Logic Memory cell have various logic between one and zero that's why fuzzy logic is also known as multiple-logic level, when the paper work was in plan originally plan was do something in Fuzzy Electronics. Lots of fuzzy systems is been developed already but from observing fuzzy flip-flops working the idea comes for the proposed work. Paper work propose designs of a new fuzzy memory cell(flip-flop) for four logic levels which can hold Logic 0, Logic 1, Logic 2 & Logic 3 total four fix logic . though fuzzy logic deals with approximate logic rather than fix proposed work has fix logic and it is the big difference between proposed work and fuzzy based memory cell. Proposed work also has design an Interfacing module between fuzzy memory with Digital) systems, just for make proposed four logic flip-flop compatible with existing binary logic based digital system application for proposed design that one can reduce the no. of wires required when to establish parallel interface with memory and also one can increase the speed or throughput of simple serial data transfer.
References
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