Research Article
Analysis and Verification of Multi-Core Enabled ESL Model using SystemC and VLang
|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 95 - Issue 26 |
| Published: June 2014 |
| Authors: Dipti Girdhar, Neeraj Sharma, Neeraj Kr. Shukla |
10.5120/16955-6886
|
Dipti Girdhar, Neeraj Sharma, Neeraj Kr. Shukla . Analysis and Verification of Multi-Core Enabled ESL Model using SystemC and VLang. International Journal of Computer Applications. 95, 26 (June 2014), 1-4. DOI=10.5120/16955-6886
@article{ 10.5120/16955-6886,
author = { Dipti Girdhar,Neeraj Sharma,Neeraj Kr. Shukla },
title = { Analysis and Verification of Multi-Core Enabled ESL Model using SystemC and VLang },
journal = { International Journal of Computer Applications },
year = { 2014 },
volume = { 95 },
number = { 26 },
pages = { 1-4 },
doi = { 10.5120/16955-6886 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2014
%A Dipti Girdhar
%A Neeraj Sharma
%A Neeraj Kr. Shukla
%T Analysis and Verification of Multi-Core Enabled ESL Model using SystemC and VLang%T
%J International Journal of Computer Applications
%V 95
%N 26
%P 1-4
%R 10.5120/16955-6886
%I Foundation of Computer Science (FCS), NY, USA
Abstract
Today most of the system on chip (Soc) integrate multiple processing cores, digital signal processors, as well as dedicated hardware accelerators, etc [1]. This results into large and complex systems which pose challenges to conventional design and verification flow. This raises the need for higher level of abstraction (i. e. Electronics system level abstraction). This paper discusses how we can make changes in an existing conventional method of simulation to achieve really fast high yielding method of verification. The model is implemented using SystemC and Vlang. The results demonstrate the impact of enabling multiple simulators for verification of hardware models.
References
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