Abstract

Rapidly increasing design complexity due to small size and higher speed, results in the problem of clock skew and insertion delay. These are the two important parameters which should be considered for successful completion of the design. In this work, a method for minimizing clock skew by buffer insertion and resize is proposed. Clock skew will be minimized during post-CTS timing analysis after placement of standard cells during physical implementation of the design. Also, buffer relocation method is used for minimizing the delay of the cells. Simulations were carried out on EDA tools and results show that overall skew is improved by 23. 95% and delay is improved by 19. 50%.

References

• Weixiang Shena, Yici Cai, Wei Chen, Yongqiang Lu, Qiang Zhou and Jiang Hue, 2010, "Useful Clock Skew Optimization under A Multi-corner Multi-mode Design Framework," in proceedings of 11th International Symposium on Quality Electronic Design (ISQED), 2010, pp. 62-68.
• Chiao-Ling Lung, Hai-Chi Hsiao, Zi-Yi Zeng, and Shih-Chieh Chang, "LP-Based Multi-Mode Multi-Corner Clock Skew Optimization," in proceedings of International Symposium on VLSI Design Automation and Test (VLSI-DAT), April 2010, pp. 335-338.
• Haihua Su and Sachin S. Sapatnekar. "Hybrid structured clock network construction," in Proceedings of the 2001 IEEE/ACM International Conference on Computer-aided design, pp. 333–336, 2001.
• Patrick Mahoney, Eric Fetzer, Bruce Doyle, and Sam Naffziger, "Clock distribution on a dual-core multithreaded Itanium-family processor," in Digest of technical papers of the 2005 international solid-state circuits conference, pp. 292–293, 2005.
• R. -S. Tsay, "Exact zero skew," In Proceedings of the 1991 IEEE international conference on Computer-aided design, pp. 336–339, 1991.
• Ting-Hai Chao, Yu-Chin Hsu, Jan-Ming Ho, and A. B. Kahng, "Zero skew clock routing with minimum wirelength," Circuits and Systems II: Analog and Digital Signal Processing, Vol. 39, No. 11, pp. 799–814, Nov. 1992.
• Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, and C. -W. Albert Tsao, "Bounded-skew clock and steiner routing," ACM Transactions on Design Automatic Electronic System, Vol. 3, No. 3, 1998.
• Chung wen Albert Tsao and Cheng Kok Koh, "UST/DME: a clock tree router for general skew constraints" ACM Transactions on Design Automatic Electronic System, Vol. 7, No. 3, pp. 359–379, 2002.
• Shen Lin and C. K. Wong, "Process-variation-tolerant clock skew minimization," in proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, pp. 284–288, 1994.
• L. P. P. P. Van Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay," in proceedings of the IEEE International Symposium on Circuits and Systems, pp. 865–868, 1990.
• John Lillis, Chung-Kuan Cheng, and Ting-Ting Y. Lin, "Optimal wire sizing and buffer insertion for low power and a generalized delay model," in proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, pp. 138–143, 1995.
• Takumi Okamoto and Jason Cong, "Buffered Steiner tree construction with wire sizing for interconnect layout optimization," in proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, pp. 44–49, 1996.
• Charles J. Alpert, Anirudh Devgan, and Stephen T. Quay, "Buffer insertion with accurate gate and interconnect delay computation," in proceedings of the 36th annual conference on Design automation, pp. 479–484, 1999.
• Y. -P. Chen and D. F. Wong, "An algorithm for zero-skew clock tree routing with buffer insertion," in proceedings of the European Design and Test Conference, pp. 230–236, 1996.
• A. Vittal and M. Marek-Sadowska, "Power optimal buffered clock tree design," in proceedings of the Design automation conference, pp. 230–236, 1996.
• I-Min Liu, Tan-Li Chou, Adnan Aziz, and D. F. Wong, "Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion," in proceedings of the international symposium on Physical design, 2000, pp. 33–38, 2000.
• Hsiao-Pin Su, Wu, A. C. -H. , Youn-Long Lin, "A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning," in proceedings of the 36th conference on Design automation, June 1999, pp. 262-267.
• Rony Kay, Gennady Bucheuv, and Lawrence T. Pileggi. EWA: exact wiring-sizing algorithm," in proceedings of the International Symposium on Physical design, 1997, pp. 178–185.
• Jason Cong, Cheng-Kok Koh, and Kwok-Shing Leung, "Simultaneous buffer and wire sizing for performance and power optimization," in proceedings of the 1996 international symposium on Low power electronics and design, 1996, pp. 271–276.
• Chung-Ping Chen, Chris C. N. Chu, and D. F. Wong, "Fast and exact simultaneous gate and wire sizing by lagrangian relaxation," in proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, 1998, pp. 617–624.
• Satyamurthy Pullela, Noel Menezes, and Lawrence T. Pillage, "Reliable non-zero skew clock trees using wire width optimization," in proceedings of the 30th annual conference on Design automation, 1993, pp. 165–170.
• X. Zeng, D. Zhou, and Wei Li, "Buffer insertion for clock delay and skew minimization," in proceedings of the 1999 international symposium on Physical design, 1999, pp. 36–41.
• Chung-Ping Chen, Yao-Wen Chang, and D. F. Wong, "Fast performance-driven optimization for buffered clock trees based on lagrangian relaxation," in proceedings of the 33rd annual conference on Design automation, 1996, pp. 405–408.
• Charles E. Leiserson, Flavio M. Rose, and James B. Saxe, "Optimizing synchronous circuitry by retiming," In proceedings of the 3rd CalTech conference on Very Large Scale Integration, March 1983, pp. 87–116.
• L. W. Cotton, "Circuit implementation of high-speed pipeline systems," in proceedings of the AFIPS Fall Joint Computer Conference, 1965, pp. 489–504.
• John P. Fishburn, "Clock skew optimization," IEEE Transactions on Computers, July 1990, Vol. 39, No. 7, pp. 945–951.
• Rahul B. Deokar and Sachin S. Sapatnekar, "A graph-theoretic approach to clock skew optimization," in proceedings of the 1994 IEEE International Symposium on Circuits and Systems, May 1995, Vol. 1, pp. 407–410.
• Jose Luis Neves and Eby G. Friedman, "Optimal clock skew scheduling tolerant to process variations," in proceedings of the 33rd annual conference on Design automation, 1996, pp. 623–628.
• Ivan S. Kourtev and Eby G. Friedman. "Clock skew scheduling for improved reliability via quadratic programming," in proceedings of the 1999 IEEE/ACM International Conference on Computer-aided design, 1999, pp. 239–243.
• Xun Liu, Marios C. Papaefthymiou, and Eby G. Friedman, "Maximizing performance by retiming and clock skew scheduling," in proceedings of the 36th annual conference on Design automation, 1999, pp. 231–236.
• Baris Taskin and Ivan S. Kourtev, "Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew," in proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems, 2002, pp. 111–118.
• C. Albrecht, B. Korte, J. Schietke, and J. Vygen, "Cycle time and slack optimization for vlsi-chips," in proceedings of the 1999 IEEE/ACM International Conference on Computer-aided design, pp. 232–238.
• Stephan Held, Bernhard Korte, Jens Maberg, Matthias Ringe, and J. Vygen, "Clock scheduling and clock tree construction for high performance ASICs," in proceedings of the 2003 IEEE/ACM international conference on Computer-Aided design, 2003, pp. 232–239.
• R. Bellman, "On a routing problem," Quarterly of Applied Mathematics, 1958, Vol. 6, No. 1, pp. 87–90.
• L. R. Ford and D. R. Fulkerson, "Flows in networks," Princeton University Press, 1962.
• N. E. Young, Robert E. Tarjan, and J. B. Orlin, "Faster parametric shortest path and minimum-balance algorithms," Networks, 1991, Vol. 21, pp. 205–221.
• Cadence's "SOC Encounter RTL to GDSII System Datasheet" available on URL: http://www. cadence. com/products/di/soc_encounter/pp. /default. aspx
• Cadence's "Encounter RTL Compiler Datasheet" available on URL: http://www. cadence. com/products/ld/rtl_compiler/pp. /default. aspx
• Video Tutorial "Place and Route with Cadence SOC Encounter (Basics)" Online available at URL:http://www. youtube. com/watch?v=Z5WKIDbthdg.
• X. Zeng, D. Zhou, Wei Li, "Buffer Insertion for Clock Delay and Skew Minimization," in proceedings of the International Symposium on Physical design, New York, 1999, pp. 36-41.
• Shih-Heng Tsai, Man-Yu Li, and Chung-Yang (Ric) Huang, 2012, "A Semi-Formal Min-Cost Buffer Insertion Technique Considering Multi-Mode Multi-Corner Timing Constraints," in proceedings of 17th Asia and South Pacific Design Automation Conference (ASP-DAC), Feb 2012, pp. 505-510.
• Alessandro Balboni, Claudio Costi, Massimo Pellencin, Andrea Quadrini, and Donatella Sciuto, 1998, "Clock Skew Reduction in ASIC Logic Design: A Methodology for Clock Tree Management," IEEE transactions on Computer-Aided Design of integrated circuits and systems, April 1998, Vol. 17, No. 4, pp. 344-356.
• N. Parthibhan, Mr. S. Ravi, and Dr. Kittur Harish Maillikarjun, 2012, "Clock Skew Optimization in Pre and Post CTS," in proceedings of International Conference on Advances in Computing and Communications, Aug. 2012, pp. 146-149.
• Herr, Q. P. , and Bunyk, P. , 2003, "Implementation and application of first-in first-out buffers," IEEE Transactions on Applied Superconductivity, June 2003, Vol. 13 , No. 2 , pp. 563-566.
• Xin Wang, Ahonen, T. , and Nurmi, J. , 2004, "A Synthesizable RTL Design of Asynchronous FIFO," in Proceedings of International Symposium on System-on-Chip, Nov. 2004, pp. 123-128.