Research Article
Built in Self-Test for 4 × 4 Signed and Unsigned Multipliers in FPGA
|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 95 - Issue 16 |
| Published: June 2014 |
| Authors: Shrikant Vaishnav, Puran Gaur, Braj Bihari Soni |
10.5120/16681-6792
|
Shrikant Vaishnav, Puran Gaur, Braj Bihari Soni . Built in Self-Test for 4 × 4 Signed and Unsigned Multipliers in FPGA. International Journal of Computer Applications. 95, 16 (June 2014), 30-35. DOI=10.5120/16681-6792
@article{ 10.5120/16681-6792,
author = { Shrikant Vaishnav,Puran Gaur,Braj Bihari Soni },
title = { Built in Self-Test for 4 × 4 Signed and Unsigned Multipliers in FPGA },
journal = { International Journal of Computer Applications },
year = { 2014 },
volume = { 95 },
number = { 16 },
pages = { 30-35 },
doi = { 10.5120/16681-6792 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2014
%A Shrikant Vaishnav
%A Puran Gaur
%A Braj Bihari Soni
%T Built in Self-Test for 4 × 4 Signed and Unsigned Multipliers in FPGA%T
%J International Journal of Computer Applications
%V 95
%N 16
%P 30-35
%R 10.5120/16681-6792
%I Foundation of Computer Science (FCS), NY, USA
Abstract
Built in self-test (BIST) is a technique or a method which allow the circuit to test itself. BIST increases the controllability and observability of integrated circuit therefore it is easier to apply inputs and then detect faults from it [11]. BIST also decreases the time of testing integrated circuits & gives very high fault coverage. Therefore in many ways BIST help us in detecting fault in integrated circuits. This paper presents an efficient fault detection algorithm for 4 × 4 signed & unsigned multiplier in field programmable gate array (FPGA). These techniques were successfully applied on booth, braun & unsigned array multipliers.
References
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