Research Article
Low Power Domino Full Adder
|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 93 - Issue 10 |
| Published: May 2014 |
| Authors: Payal Soni, Shiwani Singh |
10.5120/16255-5866
|
Payal Soni, Shiwani Singh . Low Power Domino Full Adder. International Journal of Computer Applications. 93, 10 (May 2014), 40-43. DOI=10.5120/16255-5866
@article{ 10.5120/16255-5866,
author = { Payal Soni,Shiwani Singh },
title = { Low Power Domino Full Adder },
journal = { International Journal of Computer Applications },
year = { 2014 },
volume = { 93 },
number = { 10 },
pages = { 40-43 },
doi = { 10.5120/16255-5866 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2014
%A Payal Soni
%A Shiwani Singh
%T Low Power Domino Full Adder%T
%J International Journal of Computer Applications
%V 93
%N 10
%P 40-43
%R 10.5120/16255-5866
%I Foundation of Computer Science (FCS), NY, USA
Abstract
With the advancement of technology, power consumption and higher speed becomes major concern for VLSI systems. In this paper, a new hybrid domino XOR is proposed and compared with existing domino XOR cell. As an application of proposed XOR cell, 1-bit full adder has been designed and compared with a full adder circuit using existing XOR cell. Both proposed designs XOR and full adder show better results in terms of power, delay and power-delay product. All the simulations have been performed on 45nm technology using tanner EDA tool version 13. 0.
References
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