Research Article
FPGA Implementation of Fir Filter using Distributed Arithmetic Architecture for DWT
|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 92 - Issue 16 |
| Published: April 2014 |
| Authors: Shruti S. Velukar, M. P. Parlewar |
10.5120/16092-5363
|
Shruti S. Velukar, M. P. Parlewar . FPGA Implementation of Fir Filter using Distributed Arithmetic Architecture for DWT. International Journal of Computer Applications. 92, 16 (April 2014), 12-16. DOI=10.5120/16092-5363
@article{ 10.5120/16092-5363,
author = { Shruti S. Velukar,M. P. Parlewar },
title = { FPGA Implementation of Fir Filter using Distributed Arithmetic Architecture for DWT },
journal = { International Journal of Computer Applications },
year = { 2014 },
volume = { 92 },
number = { 16 },
pages = { 12-16 },
doi = { 10.5120/16092-5363 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2014
%A Shruti S. Velukar
%A M. P. Parlewar
%T FPGA Implementation of Fir Filter using Distributed Arithmetic Architecture for DWT%T
%J International Journal of Computer Applications
%V 92
%N 16
%P 12-16
%R 10.5120/16092-5363
%I Foundation of Computer Science (FCS), NY, USA
Abstract
This paper presents an efficient FPGA implementation of Finite Impulse Response Filter for Discrete Wavelet Transform using Distributed Arithmetic architecture. This paper proposes a parallel implementation of FIR filter using Distributed Arithmetic Architecture, Distributed Arithmetic Architecture is a multiplier less architecture which uses Look-Up Table, ripple carry adder, shift registers. Distributed Arithmetic has an advantaged of less hardware, fast computation time.
References
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