Research Article

A Load Balancer for a Multi-Stage Router Architecture

by  Shadi Atalla, Andrea Bianco, Robert Birke, Luca Giraudo
journal cover
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 89 - Issue 3
Published: March 2014
Authors: Shadi Atalla, Andrea Bianco, Robert Birke, Luca Giraudo
10.5120/15479-4193
PDF

Shadi Atalla, Andrea Bianco, Robert Birke, Luca Giraudo . A Load Balancer for a Multi-Stage Router Architecture. International Journal of Computer Applications. 89, 3 (March 2014), 1-7. DOI=10.5120/15479-4193

                        @article{ 10.5120/15479-4193,
                        author  = { Shadi Atalla,Andrea Bianco,Robert Birke,Luca Giraudo },
                        title   = { A Load Balancer for a Multi-Stage Router Architecture },
                        journal = { International Journal of Computer Applications },
                        year    = { 2014 },
                        volume  = { 89 },
                        number  = { 3 },
                        pages   = { 1-7 },
                        doi     = { 10.5120/15479-4193 },
                        publisher = { Foundation of Computer Science (FCS), NY, USA }
                        }
                        %0 Journal Article
                        %D 2014
                        %A Shadi Atalla
                        %A Andrea Bianco
                        %A Robert Birke
                        %A Luca Giraudo
                        %T A Load Balancer for a Multi-Stage Router Architecture%T 
                        %J International Journal of Computer Applications
                        %V 89
                        %N 3
                        %P 1-7
                        %R 10.5120/15479-4193
                        %I Foundation of Computer Science (FCS), NY, USA
Abstract

Multi-stage software router architectures permit to overcome several limitations inherent to single stage software routers. One of the key elements of the multi-stage architecture under study are the load balancers, which are used to distribute the load among backend routers. However, using a PC (Personal Computer) as a load balancer could create a performance bottleneck in the overall architecture. Since the operations performed by the load balancer are simple, we explore the possibility of an hardware-based implementation of load balancing functionality with the goal of improving its performance. In this paper, we describe the architecture of an FPGA-based load balancer and we present some performance results of its prototype implementation.

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Index Terms
Computer Science
Information Sciences
No index terms available.
Keywords

Load Balancer

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