Research Article

Verification IP for Routing Switch based on Network Layer Protocol, using SystemVerilog

by  Dipti Girdhar, Neeraj Sharma, Shankar
journal cover
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 85 - Issue 11
Published: January 2014
Authors: Dipti Girdhar, Neeraj Sharma, Shankar
10.5120/14888-3323
PDF

Dipti Girdhar, Neeraj Sharma, Shankar . Verification IP for Routing Switch based on Network Layer Protocol, using SystemVerilog. International Journal of Computer Applications. 85, 11 (January 2014), 33-37. DOI=10.5120/14888-3323

                        @article{ 10.5120/14888-3323,
                        author  = { Dipti Girdhar,Neeraj Sharma,Shankar },
                        title   = { Verification IP for Routing Switch based on Network Layer Protocol, using SystemVerilog },
                        journal = { International Journal of Computer Applications },
                        year    = { 2014 },
                        volume  = { 85 },
                        number  = { 11 },
                        pages   = { 33-37 },
                        doi     = { 10.5120/14888-3323 },
                        publisher = { Foundation of Computer Science (FCS), NY, USA }
                        }
                        %0 Journal Article
                        %D 2014
                        %A Dipti Girdhar
                        %A Neeraj Sharma
                        %A Shankar
                        %T Verification IP for Routing Switch based on Network Layer Protocol, using SystemVerilog%T 
                        %J International Journal of Computer Applications
                        %V 85
                        %N 11
                        %P 33-37
                        %R 10.5120/14888-3323
                        %I Foundation of Computer Science (FCS), NY, USA
Abstract

Today, in the world of ASICs and system-on-chip (SoC) designs which consists of millions of transistors and gates, verification is the process which consumes most of design efforts and time [4]. One of the major stresses for the verification engineer is to verify the given design in best possible manner [5]. For this he needs to cover almost all the hidden corners cases by applying various real time test cases. This paper will assist the verification engineers to understand the flow of verification environment for packet switch IP. We will also learn about the functional coverage. The language used for verification is SystemVerilog.

References
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Index Terms
Computer Science
Information Sciences
No index terms available.
Keywords

SystemVerilog Verification IP Packet switch

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