Research Article

Performance Analysis of Gate-All-Around Field Effect Transistor for CMOS Nanoscale Devices

by  Awanit Sharma, Shyam Akashe
journal cover
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 84 - Issue 10
Published: December 2013
Authors: Awanit Sharma, Shyam Akashe
10.5120/14616-2874
PDF

Awanit Sharma, Shyam Akashe . Performance Analysis of Gate-All-Around Field Effect Transistor for CMOS Nanoscale Devices. International Journal of Computer Applications. 84, 10 (December 2013), 44-48. DOI=10.5120/14616-2874

                        @article{ 10.5120/14616-2874,
                        author  = { Awanit Sharma,Shyam Akashe },
                        title   = { Performance Analysis of Gate-All-Around Field Effect Transistor for CMOS Nanoscale Devices },
                        journal = { International Journal of Computer Applications },
                        year    = { 2013 },
                        volume  = { 84 },
                        number  = { 10 },
                        pages   = { 44-48 },
                        doi     = { 10.5120/14616-2874 },
                        publisher = { Foundation of Computer Science (FCS), NY, USA }
                        }
                        %0 Journal Article
                        %D 2013
                        %A Awanit Sharma
                        %A Shyam Akashe
                        %T Performance Analysis of Gate-All-Around Field Effect Transistor for CMOS Nanoscale Devices%T 
                        %J International Journal of Computer Applications
                        %V 84
                        %N 10
                        %P 44-48
                        %R 10.5120/14616-2874
                        %I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper explains the performance analysis of Gate-All-Around silicon nanowire with 80nm diameter field effect transistor based CMOS based device utilizing the 45-nm technology. Simulation and analysis of nanowire (NW) CMOS inverter show that there is the reduction of 70% in leakage power and delay minimization of 25% as compared with 180 nm channel length. Gate-All-Aorund (GAA) configuration provides better and low drain induced barrier lowering (DIBL) ~63. 3mV/V and competent Subthresold slope ~95mV/V. GAA achieved the better voltage gain of ~10. 1 V/V . Static noise margin improved with 400mv. It provides high on drive current ~6mA this is validated that the threshold voltage of GAA field effect transistor.

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Index Terms
Computer Science
Information Sciences
No index terms available.
Keywords

Gate-All-Around (GAA) silicon nanowire Drain induced barrier lowering (DIBL) Metal oxide semiconductor field effect transistor (MOSFET)

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