International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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Volume 80 - Issue 15 |
Published: October 2013 |
Authors: Ambikesh Prasad Gupta, Shweta Singh, Nitin Meena |
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Ambikesh Prasad Gupta, Shweta Singh, Nitin Meena . Low Power and Area Efficient 2-D DWT Using 9/7 Filter based on NEDA Technique. International Journal of Computer Applications. 80, 15 (October 2013), 18-21. DOI=10.5120/13937-1902
@article{ 10.5120/13937-1902, author = { Ambikesh Prasad Gupta,Shweta Singh,Nitin Meena }, title = { Low Power and Area Efficient 2-D DWT Using 9/7 Filter based on NEDA Technique }, journal = { International Journal of Computer Applications }, year = { 2013 }, volume = { 80 }, number = { 15 }, pages = { 18-21 }, doi = { 10.5120/13937-1902 }, publisher = { Foundation of Computer Science (FCS), NY, USA } }
%0 Journal Article %D 2013 %A Ambikesh Prasad Gupta %A Shweta Singh %A Nitin Meena %T Low Power and Area Efficient 2-D DWT Using 9/7 Filter based on NEDA Technique%T %J International Journal of Computer Applications %V 80 %N 15 %P 18-21 %R 10.5120/13937-1902 %I Foundation of Computer Science (FCS), NY, USA
In this paper, based on word-serial pipeline architecture, a new efficient distributed arithmetic (NEDA) technique is introduced. This architecture increases the speed and reduced the time of 2-D discrete wavelet transform (DWT). In this design, word-serial pipeline architecture able to compute a complete 2-D discrete wavelet transforms (DWT) binary tree in an on-line fashion, and easily configurable in order to compute any required 2-D DWT sub tree is proposed. In this architecture, free of ROM, multiplication and subtraction, 9 high-pass and 7 low-pass NEDA techniques are used concurrently. The proposed NEDA architecture is 30% faster than compare the exiting architecture and 27% reduced the area. The word-serial pipelines architecture has 100% hardware utilization efficiency.