Research Article

Low Power and Area Efficient 2-D DWT Using 9/7 Filter based on NEDA Technique

by  Ambikesh Prasad Gupta, Shweta Singh, Nitin Meena
journal cover
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 80 - Issue 15
Published: October 2013
Authors: Ambikesh Prasad Gupta, Shweta Singh, Nitin Meena
10.5120/13937-1902
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Ambikesh Prasad Gupta, Shweta Singh, Nitin Meena . Low Power and Area Efficient 2-D DWT Using 9/7 Filter based on NEDA Technique. International Journal of Computer Applications. 80, 15 (October 2013), 18-21. DOI=10.5120/13937-1902

                        @article{ 10.5120/13937-1902,
                        author  = { Ambikesh Prasad Gupta,Shweta Singh,Nitin Meena },
                        title   = { Low Power and Area Efficient 2-D DWT Using 9/7 Filter based on NEDA Technique },
                        journal = { International Journal of Computer Applications },
                        year    = { 2013 },
                        volume  = { 80 },
                        number  = { 15 },
                        pages   = { 18-21 },
                        doi     = { 10.5120/13937-1902 },
                        publisher = { Foundation of Computer Science (FCS), NY, USA }
                        }
                        %0 Journal Article
                        %D 2013
                        %A Ambikesh Prasad Gupta
                        %A Shweta Singh
                        %A Nitin Meena
                        %T Low Power and Area Efficient 2-D DWT Using 9/7 Filter based on NEDA Technique%T 
                        %J International Journal of Computer Applications
                        %V 80
                        %N 15
                        %P 18-21
                        %R 10.5120/13937-1902
                        %I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper, based on word-serial pipeline architecture, a new efficient distributed arithmetic (NEDA) technique is introduced. This architecture increases the speed and reduced the time of 2-D discrete wavelet transform (DWT). In this design, word-serial pipeline architecture able to compute a complete 2-D discrete wavelet transforms (DWT) binary tree in an on-line fashion, and easily configurable in order to compute any required 2-D DWT sub tree is proposed. In this architecture, free of ROM, multiplication and subtraction, 9 high-pass and 7 low-pass NEDA techniques are used concurrently. The proposed NEDA architecture is 30% faster than compare the exiting architecture and 27% reduced the area. The word-serial pipelines architecture has 100% hardware utilization efficiency.

References
  • M. Alam, C. A. Rahman, and G. Jullian, "Efficient distributed arithmetic based DWT architectures for multimedia applications," in Proc. IEEE Workshop on SoC for real-time applications, pp. 333 336, 2003.
  • X. Cao, Q. Xie, C. Peng, Q. Wang and D. Yu, "An efficient VLSI implementation of distributed architecture for DWT," in Proc. IEEE Workshop on Multimedia and Signal Process. , pp. 364-367, 2006.
  • M. Martina, and G. Masera, "Low-complexity, efficient 9/7 wavelet filters VLSI implementation," IEEE Trans. on Circuits and Syst. II, Express Brief vol. 53, no. 11, pp. 1289-1293, Nov. 2006.
  • M. Martina, and G. Masera, "Multiplierless, folded 9/7-5/3 wavelet VLSI architecture," IEEE Trans. on Circuits an syst. II, Express Brief vol. 54, no. 9, pp. 770-774, Sep. 2007.
  • C. -C. Cheng, C. -T. Huang, C. -Y. Cheng, C. -Jr. Lian and L. -G. Chen, "On-chip memory optimization scheme for VLSI implementation of line-based two dimensional discrete wavelet transform," IEEE Trans. on circuit and System for Video Technology, vol. 17, no. 7, pp. 814-822, July 2007. July 2007
  • P. K. Meher, B. K. Mohanty and J. C. Patra, "Hardware- Efficient Systolic-Like Modular Design for Two-Dimensional Discrete Wavelet Transform", IEEE transactions on circuits and systems—ii: express briefs, vol. 55, no. 2, february 2008.
  • A. M. Shams, A. Chidanandan, W. Pan and M. A. Bayoumi, "NEDA: A Low-Power High-Performance DCT Architecture," IEEE Transactions on signal processing, vol. 54, no. 3, march 2006.
  • Archana Chidanandan and Magdy Bayoumi, "AREA-EFFICIENT NEDA ARCHITECTURE FOR THE 1-D DCT/IDCT," ICASSP 2006.
  • Gaurav Tewari, Santu Sardar, K. A. Babu, " High-Speed & Memory Efficient 2-D DWT on Xilinx Spartan3A DSP using scalable Polyphase Structure with DA for JPEG2000 Standard," 978-1-4244-8679-3/11/$26. 00 ©2011 IEEE.
Index Terms
Computer Science
Information Sciences
No index terms available.
Keywords

2-DDiscrete Wavelet Transform (DWT) NEDA Synopsis Simulation.

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