International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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Volume 79 - Issue 16 |
Published: October 2013 |
Authors: S. Baba Fariddin, E. Vargil Vijay |
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S. Baba Fariddin, E. Vargil Vijay . Design of Efficient 16-Bit Parallel Prefix Ladner-Fischer Adder. International Journal of Computer Applications. 79, 16 (October 2013), 10-14. DOI=10.5120/13943-1784
@article{ 10.5120/13943-1784, author = { S. Baba Fariddin,E. Vargil Vijay }, title = { Design of Efficient 16-Bit Parallel Prefix Ladner-Fischer Adder }, journal = { International Journal of Computer Applications }, year = { 2013 }, volume = { 79 }, number = { 16 }, pages = { 10-14 }, doi = { 10.5120/13943-1784 }, publisher = { Foundation of Computer Science (FCS), NY, USA } }
%0 Journal Article %D 2013 %A S. Baba Fariddin %A E. Vargil Vijay %T Design of Efficient 16-Bit Parallel Prefix Ladner-Fischer Adder%T %J International Journal of Computer Applications %V 79 %N 16 %P 10-14 %R 10.5120/13943-1784 %I Foundation of Computer Science (FCS), NY, USA
A parallel-prefix adder gives the best performance in VLSI design. However, performance of Ladner-Fischer adder through black cell takes huge memory. So, gray cell can be replaced instead of black cell which gives the Efficiency in Ladner-Fischer Adder. The proposed system consists of three stages of operations they are pre-processing stage, carry generation stage, post-processing stage. The pre-processing stage focuses on propagate and generate, carry generation stage focuses on carry generation and post-processing stage focuses on final result. In ripple carry adder each bit of addition operation is waited for the previous bit addition operation. In efficient Ladner - Fischer adder, addition operation does not wait for previous bit addition operation and modification is done at gate level to improve the speed and to decreases the memory used.