Research Article
Implementation of RS Encoder and RS Decoder using UHD Architecture
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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| Volume 78 - Issue 12 |
| Published: September 2013 |
| Authors: Naresh. B, S. Srinivas |
10.5120/13575-1308
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Naresh. B, S. Srinivas . Implementation of RS Encoder and RS Decoder using UHD Architecture. International Journal of Computer Applications. 78, 12 (September 2013), 17-23. DOI=10.5120/13575-1308
@article{ 10.5120/13575-1308,
author = { Naresh. B,S. Srinivas },
title = { Implementation of RS Encoder and RS Decoder using UHD Architecture },
journal = { International Journal of Computer Applications },
year = { 2013 },
volume = { 78 },
number = { 12 },
pages = { 17-23 },
doi = { 10.5120/13575-1308 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2013
%A Naresh. B
%A S. Srinivas
%T Implementation of RS Encoder and RS Decoder using UHD Architecture%T
%J International Journal of Computer Applications
%V 78
%N 12
%P 17-23
%R 10.5120/13575-1308
%I Foundation of Computer Science (FCS), NY, USA
Abstract
Reed Solomon (RS) codes are a sort of non-binary cyclic codes. This code is widely used in wireless and mobile communication units. RS encoder along with RS decoder using UHD architecture is designed in this paper. In this brief, a novel low complexity reformulated inverse-free burst-error correction algorithm is developed. Then based on the Proposed RiBC algorithm, a Unified VLSI architecture is designed. It will be shown that, it can achieve high-speed, throughput and improved error correcting capability than Hard Decision Decoding (HDD) design with less area. A design of (7, 3) Reed Solomon encoder and Decoder are implemented using Verilog hardware description language (HDL) code, simulated and synthesized by XILINX ISE simulator.
References
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