Abstract

In this contribution, we present microwind2 based fault simulation environment. Many faults may occur on the circuit level as well as physical level. To fulfill our goal, the layout design of BCD to Excess-3 code converter is taken and the effect of various faults such as latchup, distribution of RC effect, input waveform slope and bridging fault are seen. The effect of these faults are examined on the various foundries of cmos: 0. 12 m, 0. 18 m, 0. 25 m and 0. 8 m. Experimental and simulation results show the effect of faults on layout design.

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