Research Article

Design a Low Power ADC for Blood-Glucose Monitoring

by  Sunny Anand, V. Sulochana Verma
journal cover
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 72 - Issue 14
Published: June 2013
Authors: Sunny Anand, V. Sulochana Verma
10.5120/12564-9020
PDF

Sunny Anand, V. Sulochana Verma . Design a Low Power ADC for Blood-Glucose Monitoring. International Journal of Computer Applications. 72, 14 (June 2013), 29-33. DOI=10.5120/12564-9020

                        @article{ 10.5120/12564-9020,
                        author  = { Sunny Anand,V. Sulochana Verma },
                        title   = { Design a Low Power ADC for Blood-Glucose Monitoring },
                        journal = { International Journal of Computer Applications },
                        year    = { 2013 },
                        volume  = { 72 },
                        number  = { 14 },
                        pages   = { 29-33 },
                        doi     = { 10.5120/12564-9020 },
                        publisher = { Foundation of Computer Science (FCS), NY, USA }
                        }
                        %0 Journal Article
                        %D 2013
                        %A Sunny Anand
                        %A V. Sulochana Verma
                        %T Design a Low Power ADC for Blood-Glucose Monitoring%T 
                        %J International Journal of Computer Applications
                        %V 72
                        %N 14
                        %P 29-33
                        %R 10.5120/12564-9020
                        %I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper describes the design of a low-power CMOS based current-frequency (I–F) Analog–Digital Converter. This ADC is designed for blood-glucose monitoring. This current-frequency ADC uses nA-range input currents to set and compare voltage oscillations against a self-produced reference to resolve 0–32nA with an accuracy of 5-bits at a sampling rate of 225MHz. The comparator used is dynamic latched comparator and the 5-bit counter and 5 bit latch is used to fetching the output in parallel form. This is designed in a 0. 6?m CMOS technology supplied at 1. 8V; it operates for a range of 0. 0- 1. 8V input voltage with power consumption below 1. 1?w using Cadence tools.

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Index Terms
Computer Science
Information Sciences
No index terms available.
Keywords

Current-frequency ADC Low power Dynamic Latch comparator

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