Abstract

This paper presents an effective approach to estimate tree interconnect delays in VLSI circuit designs in deep submicron technologies at high frequencies. In this paper, a symmetrical multi-level interconnect tree network topology has been taken up which consists of elementary resistance, inductance in series with capacitance in parallel. A precise method of modeling symmetrical T-tree interconnect network is effectively examined in this paper. By moment matching fine results are obtained at frequencies as high as 2 GHz at 180 nm technology node.

References

• Kahng, A. B. ; Muddu, S. , "Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model," Design Automation, 1994. 31st Conference on , vol. , no. , pp. 563,569, 6-10 June 1994.
• Sahoo, S. ; Datta, M. ; Kar, R. , "An Explicit Delay Model for On-Chip VLSI RLC Interconnect," Devices and Communications (ICDeCom), 2011 International Conference on , vol. , no. , pp. 1,5, 24-25 Feb. 2011.
• Kahng, A. B. ; Muddu, S. , "Efficient gate delay modeling for large interconnect loads," Multi-Chip Module Conference, 1996. MCMC-96, Proceedings. , 1996 IEEE , vol. , no. , pp. 202,207, 6-7 Feb 1996.
• Ismail, Y. I. ; Friedman, E. G. , "Effects of inductance on the propagation delay and repeater insertion in VLSI circuits," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol. 8, no. 2, pp. 195,206, April 2000.
• Deodhar, V. V. ; Davis, J. A. , "Optimization of throughput performance for low-power VLSI interconnects," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol. 13, no. 3, pp. 308,318, March 2005.
• Saini, S. ; Kµmar, A. M. ; Veeramachaneni, S. ; Srinivas, M. B. , "An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects," VLSI Design, 2010. VLSID '10. 23rd International Conference on , vol. , no. , pp. 411,416, 3-7 Jan. 2010
• ITRS, "Interconnect Technology Roadmap for Semiconductors", 2011 [Online]. Available: http:// public. itrs. net
• Xiao-Chun Li; Jun-Fa Mao; Min Tang, "Accurate simulation method for interconnect trees with frequency-dependent transmission line model," Microwave Conference Proceedings, 2005. APMC 2005. Asia-Pacific Conference Proceedings, vol. 1, no. , pp. 2 pp. ,, 4-7 Dec.
• Kar, R. ; Maheshwari, V. ; Maqbool, M. ; Mondal, S. ; Mal, A. K. ; Bhattacharjee, A. K. , "Crosstalk aware bandwidth modeling for distributed on-chip RLCG interconnects using difference model approach," Computing Communication and Networking Technologies (ICCCNT), 2010 International Conference on , vol. , no. , pp. 1,5, 29-31 July 2010.
• Xiao-Chun Li; Jun-Fa Mao; Hui-Fen Huang, "Accurate analysis of interconnect trees with distributed RLC model and moment matching," Microwave Theory and Techniques, IEEE Transactions on , vol. 52, no. 9, pp. 2199,2206, Sept. 2004.
• Ismail, Y. I. ; Friedman, E. G. ; Neves, J. L. , "Repeater insertion in tree structured inductive interconnect," Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , vol. 48, no. 5, pp. 471,481, May.