Research Article
Analysis of Power Efficient Modulo 2n+1 Adder Architectures
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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| Volume 70 - Issue 4 |
| Published: May 2013 |
| Authors: M.Parimaladevi, R.Karthi |
10.5120/11948-7765
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M.Parimaladevi, R.Karthi . Analysis of Power Efficient Modulo 2n+1 Adder Architectures. International Journal of Computer Applications. 70, 4 (May 2013), 8-16. DOI=10.5120/11948-7765
@article{ 10.5120/11948-7765,
author = { M.Parimaladevi,R.Karthi },
title = { Analysis of Power Efficient Modulo 2n+1 Adder Architectures },
journal = { International Journal of Computer Applications },
year = { 2013 },
volume = { 70 },
number = { 4 },
pages = { 8-16 },
doi = { 10.5120/11948-7765 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2013
%A M.Parimaladevi
%A R.Karthi
%T Analysis of Power Efficient Modulo 2n+1 Adder Architectures%T
%J International Journal of Computer Applications
%V 70
%N 4
%P 8-16
%R 10.5120/11948-7765
%I Foundation of Computer Science (FCS), NY, USA
Abstract
Two modified architectures for modulo 2n+1 adders are introduced in this paper. Only some of the carries of modulo 2n+1 addition are computed in sparse carry computation unit present in first architecture. This sparse approach is introduced by inverted circular idempotency property of the parallel-prefix carry operator and in this modified pre-processing stage and carry select blocks are combine the multiplexer operation of a diminished-one adder can be implemented in smaller LUT's and less consumes power, while maintain the same operating speed and delay. The modulo adder 2n+1 adders can be easily derived by adding extra logic of modulo 2n-1 adders present in second architecture.
References
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