Research Article
Reduced Complexity Hybrid Ripple Carry Lookahead Adder
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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| Volume 70 - Issue 28 |
| Published: May 2013 |
| Authors: Ravish Aradhya H. V, Lakshmesha J, Muralidhara K. N |
10.5120/12254-8202
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Ravish Aradhya H. V, Lakshmesha J, Muralidhara K. N . Reduced Complexity Hybrid Ripple Carry Lookahead Adder. International Journal of Computer Applications. 70, 28 (May 2013), 13-16. DOI=10.5120/12254-8202
@article{ 10.5120/12254-8202,
author = { Ravish Aradhya H. V,Lakshmesha J,Muralidhara K. N },
title = { Reduced Complexity Hybrid Ripple Carry Lookahead Adder },
journal = { International Journal of Computer Applications },
year = { 2013 },
volume = { 70 },
number = { 28 },
pages = { 13-16 },
doi = { 10.5120/12254-8202 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2013
%A Ravish Aradhya H. V
%A Lakshmesha J
%A Muralidhara K. N
%T Reduced Complexity Hybrid Ripple Carry Lookahead Adder%T
%J International Journal of Computer Applications
%V 70
%N 28
%P 13-16
%R 10.5120/12254-8202
%I Foundation of Computer Science (FCS), NY, USA
Abstract
In this paper we discuss Hybrid Ripple Carry Lookahead Adder (HRCLA), which is a hybrid between Carry Lookahead Adder (CLA) and ripple adder (RA). In HRCLA time is traded off for area and power. HRCLA has been designed by rippling the last carry bit of a 4-bit CLA. HRCLA extracts the traits of Carry Lookahead Adders (CLA) speed and ripple adders (RA), area. A four bit proposed HRCLA has been implemented in Cadence using 45nm technology; the implementation results showed 12. 2 %Area, 4. 6 % power improvement and 14. 01 % critical path delay overhead over CLA.
References
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