International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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Volume 70 - Issue 14 |
Published: May 2013 |
Authors: Ashish Valuskar, Madhu Shandilya, Arvind Rajawat |
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Ashish Valuskar, Madhu Shandilya, Arvind Rajawat . Analysis of Mesh Topology of NoC for Blocking and Non-blocking Techniques. International Journal of Computer Applications. 70, 14 (May 2013), 35-38. DOI=10.5120/12033-8078
@article{ 10.5120/12033-8078, author = { Ashish Valuskar,Madhu Shandilya,Arvind Rajawat }, title = { Analysis of Mesh Topology of NoC for Blocking and Non-blocking Techniques }, journal = { International Journal of Computer Applications }, year = { 2013 }, volume = { 70 }, number = { 14 }, pages = { 35-38 }, doi = { 10.5120/12033-8078 }, publisher = { Foundation of Computer Science (FCS), NY, USA } }
%0 Journal Article %D 2013 %A Ashish Valuskar %A Madhu Shandilya %A Arvind Rajawat %T Analysis of Mesh Topology of NoC for Blocking and Non-blocking Techniques%T %J International Journal of Computer Applications %V 70 %N 14 %P 35-38 %R 10.5120/12033-8078 %I Foundation of Computer Science (FCS), NY, USA
Network on Chip is efficient on-chip communication architecture for system on chip architectures. It enables the integration of a large number of computational and storage blocks on a single chip. The router is the basic element of NoC. The router architecture can be used for building a NoC with standard topology with low latency and high speed. In this paper, we implement and analyze a 3x3 mesh network configuration with routers which can support simultaneous routing requests, with blocking and non blocking inputs.