Research Article
Design of High Performance and Power Efficient 16-bit Square Root Carry Select Adder using Hybrid PTL/CMOS Logic
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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| Volume 69 - Issue 10 |
| Published: May 2013 |
| Authors: Lakshay Suri, Devesh Lamba, Kunwar Kritarth, Bhavna Ghai, Geetanjali Sharma |
10.5120/11881-7696
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Lakshay Suri, Devesh Lamba, Kunwar Kritarth, Bhavna Ghai, Geetanjali Sharma . Design of High Performance and Power Efficient 16-bit Square Root Carry Select Adder using Hybrid PTL/CMOS Logic. International Journal of Computer Applications. 69, 10 (May 2013), 32-35. DOI=10.5120/11881-7696
@article{ 10.5120/11881-7696,
author = { Lakshay Suri,Devesh Lamba,Kunwar Kritarth,Bhavna Ghai,Geetanjali Sharma },
title = { Design of High Performance and Power Efficient 16-bit Square Root Carry Select Adder using Hybrid PTL/CMOS Logic },
journal = { International Journal of Computer Applications },
year = { 2013 },
volume = { 69 },
number = { 10 },
pages = { 32-35 },
doi = { 10.5120/11881-7696 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2013
%A Lakshay Suri
%A Devesh Lamba
%A Kunwar Kritarth
%A Bhavna Ghai
%A Geetanjali Sharma
%T Design of High Performance and Power Efficient 16-bit Square Root Carry Select Adder using Hybrid PTL/CMOS Logic%T
%J International Journal of Computer Applications
%V 69
%N 10
%P 32-35
%R 10.5120/11881-7696
%I Foundation of Computer Science (FCS), NY, USA
Abstract
In today's techno-savvy world the need of the hour is to develop devices which are power efficient as well as occupy very less area. VLSI circuits have proved to be the vital choice for most of the design engineers in order to reduce power consumption in any device. The most basic operation in any processor circuitry involves addition. Carry Select Adder (CSA) is a high speed adder and its structure reveals that there exists a possibility of reducing area and power dissipation of the circuit. This paper presents power and delay analysis of 16-Bit Square Root CSA implemented through Hybrid PTL/CMOS logic . It examines the performance of the proposed design in terms of area, delay, power in 90nm CMOS process technology. The result shows that proposed Square Root CSA structure is better in terms of area, power and Power Delay Product (PDP) than others.
References
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- Geetanjali Sharma, Uma Nirmal, Yogesh Mishra, "Synthesis of Hybrid PTL/CMOS Logic for Low Area/Power Applications" in proceeding of International Conference on System Dynamics and Control, India, August 2010.
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- L. Suri, D. Lamba, K. Kritarth and G. Sharma, "High Performance and Power Efficient 32-bit carry select Adder using Hybrid PTL/CMOS Logic Style, " in IEEE International Multi Conference on Automation, Computing, Control, Communication and Compressed Sensing, Kerela, India, March 2013.
- K. Saranya, "Low Power and Area-Efficient Carry elect Adder," International Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-2, Issue-6, January 2013.
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