Research Article

Design of Encryption System using NIOS II Processor

by  Madhav M. Deshpande, Meghana A. Hasamnis
journal cover
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 68 - Issue 21
Published: April 2013
Authors: Madhav M. Deshpande, Meghana A. Hasamnis
10.5120/11701-6742
PDF

Madhav M. Deshpande, Meghana A. Hasamnis . Design of Encryption System using NIOS II Processor. International Journal of Computer Applications. 68, 21 (April 2013), 8-13. DOI=10.5120/11701-6742

                        @article{ 10.5120/11701-6742,
                        author  = { Madhav M. Deshpande,Meghana A. Hasamnis },
                        title   = { Design of Encryption System using NIOS II Processor },
                        journal = { International Journal of Computer Applications },
                        year    = { 2013 },
                        volume  = { 68 },
                        number  = { 21 },
                        pages   = { 8-13 },
                        doi     = { 10.5120/11701-6742 },
                        publisher = { Foundation of Computer Science (FCS), NY, USA }
                        }
                        %0 Journal Article
                        %D 2013
                        %A Madhav M. Deshpande
                        %A Meghana A. Hasamnis
                        %T Design of Encryption System using NIOS II Processor%T 
                        %J International Journal of Computer Applications
                        %V 68
                        %N 21
                        %P 8-13
                        %R 10.5120/11701-6742
                        %I Foundation of Computer Science (FCS), NY, USA
Abstract

The use of embedded systems in various applications has increased extensively over last few years. Embedded systems allow hardware & software go hand in hand to perform some specific task. As the application demand goes on increasing with the time the complexity of the embedded system increases. At the same time, the size of integrated circuits should be limited considering the basic criteria for embedded system like, quality of system, quantity of system, speed of system, Performance of system and Power consumption of system. While designing system according to this criterion complexity of the system increases. To reduce complexity of system, it is designed using balanced hardware & software flow of design. This combined design of hardware & software is known as Co-Design. Using this approach we build dedicated software and hardware units on the single chip i. e. SoC design.

References
  • Ernst, R. : "Co-design of embedded systems: status and trends", Proceedings of IEEE Design and Test, April–June 1998, pp. 45–54
  • Subrahmanyam, P. A. , "Hardware-Software Co-design -- Cautious optimism for the future", Hot Topics, IEEE Computer, R. D. Williams, ed. , January, 1993, pp. 84
  • Y. Li, T. Callahan, E. Darnell, R. Harr, U. Kurkure, and J. Stockwood, "Hardware–Software Codesign of Embedded Reconfigurable Architectures", in Proc. Design Automation Conference, 2000.
  • Jason G. Tong, Ian D. L. Anderson and Mohammed A. S. Khalid: Soft-Core Processors for Embedded Systems, the 18th International Conference on Microelectronics (ICM) 2006
  • Summa Cum Laude Thesis Bhavya Daya Bachelor of Science in Electrical Engineering Bachelor of Science in Computer Engineering, Spring 2009, " RAPID PROTOTYPING OF EMBEDDED SYSTEMS USING FIELD PROGRAMMABLE GATE ARRAYS".
  • "NIOS II Processor Handbook", Altera Corporation, October 2008
  • DAEMEN, J. —RIJMEN, V. : AES Proposal: Rijndael, The Rijndael Block Cipher, AES Proposal, pp. 1–45, 1999 (http://csrc. nist. gov/CryptoToolkit/aes/).
  • Marko Mali-Fran Novak-Anton Biasizzo,"HARDWARE IMPLEMENTATION OF AES ALGORITHM", Journal of ELECTRICAL ENGINEERING, VOL. 56, NO. 9-10, 2005, 265–269
  • J. Zambreno, D. Nguyen and A. Choudhary, "Exploring area/delay tradeoffs in an AES FPGA implementation", in Proc. of International Conference on Field Programmable Logic and its Applications, Lecture Notes in Computer Science, Springer-Verlag, Vol. 3203, pp. 575-585, 2004.
  • Shrivathsa Bhargav, Larry Chen, Abhinandan Majumdar, Shiva Ramudit "128-bit AES decryption" Project report, CSEE 4840 – Embedded System Design Spring 2008, Columbia University.
  • Behrouz A. Forouzan and Debdeep Mukhopadhyay "Cryptography and Network Security" (2nd edition).
  • Shrivathsa Bhargav, Larry Chen, Abhinandan Majumdar, Shiva Ramudit "128-bit AES decryption" Project report,CSEE 4840 – Embedded System Design Spring 2008, Columbia University.
  • Behrouz A. Forouzan and Debdeep Mukhopadhyay "Cryptography and Network Security" (2nd edition).
  • William stallings "Cryptography and Network Security" 3rd Edition published by Pearson Education Inc and Dorling Kindersley Publishing Inc. Advanced Encryption Standard (AES), Nov. 26, 2001.
  • Stallings W. "Cryptography and Network Security: Principles and Practices. "4th ed. , Pearson Education,Inc. pp. 63-173. 2006.
  • Kazi Shabbir Ahmed, Md. Liakot Ali, Mohammad Bozlul Karim and S. M. Tofayel Ahmad, Institute of Information and Communication Technology Bangladesh University of Engineering and Technology, Bangladesh, " FPGA IMPLEMENTATION OF AN AES PROCESSOR".
  • Altera Corporation, "NIOS Embedded Processor System Development," [Online Document], Available HTTP:http://www. altera. com/products/ip/processors/nios/nio -index. html
  • "Custom Instruction User Guide", January 2011, Altera Corporation
  • "SOPC Builder User Guide", December 2010, Altera Corporation
  • "NIOS II Software Developer's Handbook", May 2011, Altera Corporation
  • Nios II Hardware Development Tutorial, altera, December 2009 Altera Corporation Website, www. altera. com, June 2006
  • Altera Corporation, "Nios Software Development Tutorial," [Online Document], 2003 July, [Cited 2004 March 1], Available HTTP: http://www. altera. com/literature/tt/tt_nios_sw. pdf
  • Altera Corporation, "Quartus II Development Software Handbook v4. 0," [Online Document], 2004 February, [Cited 2004 February5], Available HTTP http://www. altera. com/literature/hb/qts/quartusii_handbook. pdf
  • Altera Corporation, "Introduction to Quartus II," [Online Document], 2004 January, [Cited 2004 February 6], Available HTTP: http://www. altera. com/literature/manual/intro_to_quartus2. pdf
  • Cyclone II Device Handbook, Volume 1, AlteraCorporation
  • DE2 Development and Education Board, Altera Corporation
Index Terms
Computer Science
Information Sciences
No index terms available.
Keywords

Co-Design image processing DCT(Discrete cosine transform) Custom instruction

Powered by PhDFocusTM