International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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Volume 68 - Issue 16 |
Published: April 2013 |
Authors: Navdeep Kaur, Rajeev Kumar Patial |
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Navdeep Kaur, Rajeev Kumar Patial . Implementation of Modified Booth Multiplier using Pipeline Technique on FPGA. International Journal of Computer Applications. 68, 16 (April 2013), 38-41. DOI=10.5120/11666-7261
@article{ 10.5120/11666-7261, author = { Navdeep Kaur,Rajeev Kumar Patial }, title = { Implementation of Modified Booth Multiplier using Pipeline Technique on FPGA }, journal = { International Journal of Computer Applications }, year = { 2013 }, volume = { 68 }, number = { 16 }, pages = { 38-41 }, doi = { 10.5120/11666-7261 }, publisher = { Foundation of Computer Science (FCS), NY, USA } }
%0 Journal Article %D 2013 %A Navdeep Kaur %A Rajeev Kumar Patial %T Implementation of Modified Booth Multiplier using Pipeline Technique on FPGA%T %J International Journal of Computer Applications %V 68 %N 16 %P 38-41 %R 10.5120/11666-7261 %I Foundation of Computer Science (FCS), NY, USA
This paper presents 16×16 bit Radix-4 Modified Booth's Multiplier (MBM) optimized for high speed multiplication by using pipeline Technique. This paper aims at reduction of hardware utilization. This is accomplished by the use of 3:2 compressor adders. An efficient VHDL code has been written, successfully simulated on Modelsim 10. 2 simulator and Xilinx 12. 4 navigator is used for synthesizing the code. Simulation result shows the clock period of 2. 689ns. The selected device to synthesize the code is xc3s500e-4pq208 of Sartan-3E family. The area utilization is shown as 222 numbers of slices and 383 numbers of LUTs.