International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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Volume 66 - Issue 13 |
Published: March 2013 |
Authors: Riya Garg, Suman Nehra, B. P. Singh |
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Riya Garg, Suman Nehra, B. P. Singh . A New Design of Full Adder based on XNOR-XOR Circuit. International Journal of Computer Applications. 66, 13 (March 2013), 7-10. DOI=10.5120/11142-6224
@article{ 10.5120/11142-6224, author = { Riya Garg,Suman Nehra,B. P. Singh }, title = { A New Design of Full Adder based on XNOR-XOR Circuit }, journal = { International Journal of Computer Applications }, year = { 2013 }, volume = { 66 }, number = { 13 }, pages = { 7-10 }, doi = { 10.5120/11142-6224 }, publisher = { Foundation of Computer Science (FCS), NY, USA } }
%0 Journal Article %D 2013 %A Riya Garg %A Suman Nehra %A B. P. Singh %T A New Design of Full Adder based on XNOR-XOR Circuit%T %J International Journal of Computer Applications %V 66 %N 13 %P 7-10 %R 10.5120/11142-6224 %I Foundation of Computer Science (FCS), NY, USA
This paper presents pre-layout simulations of a proposed 8T full adder design using a proposed 3T XNOR gate cell. The proposed design remarkably reduces power consumption hence power-delay product (PDP) over various input voltages and frequencies. It also improves temperature sustainability as compared to the existing 8T full adder. This proves to be a viable option for low power and energy efficient applications. It also shows nearly 82% improvement in threshold loss as compared to the existing 8T full adder. All simulations have been performed on 45nm standard model on Tanner EDA tool version 12. 6.