Research Article
Design of New Low Leakage Power Domino XOR Circuit
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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| Volume 65 - Issue 1 |
| Published: March 2013 |
| Authors: Amit Kumar Pandey, Jayant Kumar Tiwari, Ram Awadh Mishra, Rajendra Kumar Nagaria, Manish Tiwari |
10.5120/10890-5787
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Amit Kumar Pandey, Jayant Kumar Tiwari, Ram Awadh Mishra, Rajendra Kumar Nagaria, Manish Tiwari . Design of New Low Leakage Power Domino XOR Circuit. International Journal of Computer Applications. 65, 1 (March 2013), 28-32. DOI=10.5120/10890-5787
@article{ 10.5120/10890-5787,
author = { Amit Kumar Pandey,Jayant Kumar Tiwari,Ram Awadh Mishra,Rajendra Kumar Nagaria,Manish Tiwari },
title = { Design of New Low Leakage Power Domino XOR Circuit },
journal = { International Journal of Computer Applications },
year = { 2013 },
volume = { 65 },
number = { 1 },
pages = { 28-32 },
doi = { 10.5120/10890-5787 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2013
%A Amit Kumar Pandey
%A Jayant Kumar Tiwari
%A Ram Awadh Mishra
%A Rajendra Kumar Nagaria
%A Manish Tiwari
%T Design of New Low Leakage Power Domino XOR Circuit%T
%J International Journal of Computer Applications
%V 65
%N 1
%P 28-32
%R 10.5120/10890-5787
%I Foundation of Computer Science (FCS), NY, USA
Abstract
In this paper, a new XOR gate is proposed. Proposed circuit adopts mixed N-type and P-type transistors in the pull down network and current mirror at the footer transistor. This topology reduces leakage power consumption. Simulation parameters are measured at 25°C and 110°C. Proposed circuit reduces leakage power consumption up to 51. 7% at 25°C and 56% at 110°C as compared to standard N-type domino XOR gate. Similarly, proposed circuit reduces leakage power consumption up to 47. 28% at 25°C and 51. 1% at 110°C as compared to standard P-type domino XOR gate.
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