International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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Volume 64 - Issue 12 |
Published: February 2013 |
Authors: Disha S. Aherrao, S. W. Varade |
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Disha S. Aherrao, S. W. Varade . Design and Simulation of High Speed, Low Powered ADC for Serial link Receiver. International Journal of Computer Applications. 64, 12 (February 2013), 1-4. DOI=10.5120/10683-5570
@article{ 10.5120/10683-5570, author = { Disha S. Aherrao,S. W. Varade }, title = { Design and Simulation of High Speed, Low Powered ADC for Serial link Receiver }, journal = { International Journal of Computer Applications }, year = { 2013 }, volume = { 64 }, number = { 12 }, pages = { 1-4 }, doi = { 10.5120/10683-5570 }, publisher = { Foundation of Computer Science (FCS), NY, USA } }
%0 Journal Article %D 2013 %A Disha S. Aherrao %A S. W. Varade %T Design and Simulation of High Speed, Low Powered ADC for Serial link Receiver%T %J International Journal of Computer Applications %V 64 %N 12 %P 1-4 %R 10.5120/10683-5570 %I Foundation of Computer Science (FCS), NY, USA
This paper presents design & Simulation of High Speed, Low Powered ADC for Serial link Receiver. This ADC based receiver uses a low gain analog and mixed mode pre-equalizer in conjunction with the non-uniform reference levels for ADC. This combination compensates for both front-end non-ideality and the channel response while maintaining low ADC resolution and hence enables low power consumption. This receiver is based on a low power design of Analog to Digital converter, thus lowering the power consumption of overall system. Tanner tool 13. 0 is used for the simulation of the proposed design. From the simulation results it has been observed that the modules used in the proposed ADC lowers the power consumption.