Research Article
Design and Simulation of Low power CMOS Adder Cell at 180nm using Tanner Tool
|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 62 - Issue 16 |
| Published: January 2013 |
| Authors: Chakshu Goel, Puneet Jain, Gurjeevan Singh |
10.5120/10166-4958
|
Chakshu Goel, Puneet Jain, Gurjeevan Singh . Design and Simulation of Low power CMOS Adder Cell at 180nm using Tanner Tool. International Journal of Computer Applications. 62, 16 (January 2013), 30-33. DOI=10.5120/10166-4958
@article{ 10.5120/10166-4958,
author = { Chakshu Goel,Puneet Jain,Gurjeevan Singh },
title = { Design and Simulation of Low power CMOS Adder Cell at 180nm using Tanner Tool },
journal = { International Journal of Computer Applications },
year = { 2013 },
volume = { 62 },
number = { 16 },
pages = { 30-33 },
doi = { 10.5120/10166-4958 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2013
%A Chakshu Goel
%A Puneet Jain
%A Gurjeevan Singh
%T Design and Simulation of Low power CMOS Adder Cell at 180nm using Tanner Tool%T
%J International Journal of Computer Applications
%V 62
%N 16
%P 30-33
%R 10.5120/10166-4958
%I Foundation of Computer Science (FCS), NY, USA
Abstract
In this Research Paper, the focus is on the analysis and simulation of the Adder cell which is slightly different as compared to the existing circuits and optimized for Average Power Dissipation. In this paper the adder cell is modified circuit in such a way that it controls the overall capacitances during the Sum and Carry evaluation and will optimize the total capacitance that results in the decrease of the Average Power dissipation. The circuit is characterized by using HSPICE in a 180 nanometer (nm) with supply voltage of 1. 8 volt and threshold voltage is 0. 40 volts.
References
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