Research Article

Optimization of Pie-gate Bulk FinFET Structure

by  S. L. Tripathi, Ramanuj Mishra, Narendra Vadthiya, R. A. Mishra
journal cover
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 59 - Issue 2
Published: December 2012
Authors: S. L. Tripathi, Ramanuj Mishra, Narendra Vadthiya, R. A. Mishra
10.5120/9522-3930
PDF

S. L. Tripathi, Ramanuj Mishra, Narendra Vadthiya, R. A. Mishra . Optimization of Pie-gate Bulk FinFET Structure. International Journal of Computer Applications. 59, 2 (December 2012), 34-39. DOI=10.5120/9522-3930

                        @article{ 10.5120/9522-3930,
                        author  = { S. L. Tripathi,Ramanuj Mishra,Narendra Vadthiya,R. A. Mishra },
                        title   = { Optimization of Pie-gate Bulk FinFET Structure },
                        journal = { International Journal of Computer Applications },
                        year    = { 2012 },
                        volume  = { 59 },
                        number  = { 2 },
                        pages   = { 34-39 },
                        doi     = { 10.5120/9522-3930 },
                        publisher = { Foundation of Computer Science (FCS), NY, USA }
                        }
                        %0 Journal Article
                        %D 2012
                        %A S. L. Tripathi
                        %A Ramanuj Mishra
                        %A Narendra Vadthiya
                        %A R. A. Mishra
                        %T Optimization of Pie-gate Bulk FinFET Structure%T 
                        %J International Journal of Computer Applications
                        %V 59
                        %N 2
                        %P 34-39
                        %R 10.5120/9522-3930
                        %I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper we propose a novel Pie gate bulk FinFET structure for logic applications suitable for system-on-chip (SOC) requirements. The influence of gate at bottom to junction depth, misalignment was examined for deeper junctions and shallower junctions. It has shown that bulk FinFET with source/drain to body (S/D) junctions shallower than gate at bottom has equal or better subthreshold performance than SOI FinFET. Further, we extend the concept of heavy body doping in bulk FinFETs of Pie-gate structure. The characteristics of such bulk FinFET structure is analyzed by 3D device simulation and compared with SOI FinFET.

References
  • Jean-Pierre Colinge, "Multiple-gate SOI MOSFETs" Solid-State Electronics 48 (2004) 897–905
  • D. Hisamoto, W. C. Lee, J. Kedzierski, J. Bokor, and C. Hu, "FinFET—A self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron. Devices, vol. 47, no. 12, pp. 2320–2325, Dec. 2000.
  • D. Hisamoto, L. Wen-Chin, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, et al. ,IEEE Transactions on Electron Devices 47 (12) (2000) 2320–2325.
  • S. -K. Sung, S. -H. Lee, B. -Y. Choi, J. J. Lee, J. -D. Choe, E. S. Cho, et al. , in: VLSI Technology Symposium 2006, Digest of Technical Papers, 2006, pp. 86–87.
  • T. -S. Park, S. Choi, D. -H. Lee, U. -I. Chung, J. T. Moon, E. Yoon, et al. , Solid-State Electronics 49 (3) (2005) 377–383.
  • H. Lee, C. -H. Lee, D. Park, Y. -K. Choi, IEEE Electron Device Letters 26 (2005)326–328.
  • X. Huang, W. -C. Lee, D. H. L. Chang, J. Boker, T. J. King, V. Subramanian, and C. Hu, "Sub 50 nm P channel FinFETs," IEEE Trans. Electron. Devices, vol. 48, no. 5, pp. 880–886, May 2001.
  • E. J. Nowak, I. Aller, T. Ludwig, K. Kim, R. V. Joshi, C. -T. Chung,K. Bernstein, and R. Puri, "Turning silicon on its edge," IEEE Circuits Devices Mag. , vol. 20, no. 1, pp. 20–31, Jan. /Feb. 2004.
  • N. Bresson, S. Cristoloveanu, C. Mazure, F. Letertre, and H. Iwai, "Integration of buried insulators with high thermal conductivity in SOI MOSFETs:Thermal properties and short channel effects," Solid-State Electron. ,vol. 49, pp. 1522–1528, 2005.
  • "SOI vs. Bulk FinFET: Body Doping and Corner Effects Influence on Device Characteristics" Mirko Poljak, Vladimir Jovanovi?, and Tomislav Suligoj, IEEE ,2008
  • K. Okano, T. Izumida, H. Kawasaki, A. Kaneko, A. Yagishita, T. Kanemura, M. Kondo, S. Ito, N. Aoki, K. Miyano, T. Ono, K. Yahashi,K. Iwade, T. Kubota, T. Matsushita, I. Mizushima, S. Inaba, K. Ishimaru,K. Suguro, K. Eguchi, Y. Tsunashima, and H. Ishiuchi, "Process integrationtechnology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length," in IEDM Tech. Dig. , 2005, pp. 243–246.
  • T. Kanemura, T. Izumida, N. Aoki, M. Kondo, S. Ito, T. Enda, K. Okano, H. Kawasaki, A. Yagishita, A. Kaneko, S. Inaba,M. Nakamura, K. Ishimaru, K. Suguro, K. Eguchi, and H. Ishiuchi, "Improvement of drive current in bulk-FinFET using full 3D process/device simulations," in Proc. SISPAD 2006, pp. 131–134.
  • T. -S. Park, S. Choi,D. -H. Lee, U. -I. Chung, J. T. Moon, E. Yoon, and J. -H. Lee,"Body-tied triple-gate NMOSFET fabrication using bulk Si wafer," Solid-State Electron. , vol. 49, pp. 377–383, 2005.
  • C. R. Manoj, Meenakshi Nagpal, Dhanya Varghese, and V. Ramgopal Rao "Device Design and Optimization Considerations for Bulk FinFETs" IEEE Transactions on Electron Devices, Vol. 55, no. 2, February 2008
  • Mirko Poljak , Vladimir Jovanovic , Tomislav Suligoj "Improving bulk FinFET DC performance in comparison to SOI FinFET" Journal of Microelectronic Engineering 86 (2009) 2078–2085
  • "Sentaurus Structure Editor User's Manual", Synopsys International
  • International Technology Roadmap for Semiconductors (ITRS), 2007 Edition. www. itrs. net
Index Terms
Computer Science
Information Sciences
No index terms available.
Keywords

Shallower junction Punchthrough stopper pie gate structure

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