International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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Volume 59 - Issue 2 |
Published: December 2012 |
Authors: S. L. Tripathi, Ramanuj Mishra, Narendra Vadthiya, R. A. Mishra |
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S. L. Tripathi, Ramanuj Mishra, Narendra Vadthiya, R. A. Mishra . Optimization of Pie-gate Bulk FinFET Structure. International Journal of Computer Applications. 59, 2 (December 2012), 34-39. DOI=10.5120/9522-3930
@article{ 10.5120/9522-3930, author = { S. L. Tripathi,Ramanuj Mishra,Narendra Vadthiya,R. A. Mishra }, title = { Optimization of Pie-gate Bulk FinFET Structure }, journal = { International Journal of Computer Applications }, year = { 2012 }, volume = { 59 }, number = { 2 }, pages = { 34-39 }, doi = { 10.5120/9522-3930 }, publisher = { Foundation of Computer Science (FCS), NY, USA } }
%0 Journal Article %D 2012 %A S. L. Tripathi %A Ramanuj Mishra %A Narendra Vadthiya %A R. A. Mishra %T Optimization of Pie-gate Bulk FinFET Structure%T %J International Journal of Computer Applications %V 59 %N 2 %P 34-39 %R 10.5120/9522-3930 %I Foundation of Computer Science (FCS), NY, USA
In this paper we propose a novel Pie gate bulk FinFET structure for logic applications suitable for system-on-chip (SOC) requirements. The influence of gate at bottom to junction depth, misalignment was examined for deeper junctions and shallower junctions. It has shown that bulk FinFET with source/drain to body (S/D) junctions shallower than gate at bottom has equal or better subthreshold performance than SOI FinFET. Further, we extend the concept of heavy body doping in bulk FinFETs of Pie-gate structure. The characteristics of such bulk FinFET structure is analyzed by 3D device simulation and compared with SOI FinFET.