International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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Volume 58 - Issue 1 |
Published: November 2012 |
Authors: S. V. Padmajarani, M. Muralidhar |
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S. V. Padmajarani, M. Muralidhar . Design and implementation of a Hybrid High Speed Area Efficient Parallel Prefix Adder in an FPGA. International Journal of Computer Applications. 58, 1 (November 2012), 17-21. DOI=10.5120/9246-3410
@article{ 10.5120/9246-3410, author = { S. V. Padmajarani,M. Muralidhar }, title = { Design and implementation of a Hybrid High Speed Area Efficient Parallel Prefix Adder in an FPGA }, journal = { International Journal of Computer Applications }, year = { 2012 }, volume = { 58 }, number = { 1 }, pages = { 17-21 }, doi = { 10.5120/9246-3410 }, publisher = { Foundation of Computer Science (FCS), NY, USA } }
%0 Journal Article %D 2012 %A S. V. Padmajarani %A M. Muralidhar %T Design and implementation of a Hybrid High Speed Area Efficient Parallel Prefix Adder in an FPGA%T %J International Journal of Computer Applications %V 58 %N 1 %P 17-21 %R 10.5120/9246-3410 %I Foundation of Computer Science (FCS), NY, USA
Parallel prefix adder is the most flexible and widely used for binary addition. Parallel Prefix adders are best suited for VLSI implementation. A number of parallel prefix adder structures have been proposed over the past years intended to optimize area, fan-out, logic depth and inter connect count. This paper presents a hybrid high speed and area efficient adder architecture, based on parallel prefix computation by using four operators namely black, gray, O3-black and O3-gray operators. These operators are designed using multiplexers. The proposed hybrid architecture is implemented with 16-bit width operands on Xilinx Spartan 3E FPGA. The experimental results indicate that the proposed architecture is much faster and area efficient.