Research Article

VLSI Implementation of 4-bit 50Gbps High Speed Pipelined ADC Architecture for I-UWB Receiver

by  K. Lokesh Krishna, T. Ramashri
journal cover
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 57 - Issue 15
Published: November 2012
Authors: K. Lokesh Krishna, T. Ramashri
10.5120/9193-3621
PDF

K. Lokesh Krishna, T. Ramashri . VLSI Implementation of 4-bit 50Gbps High Speed Pipelined ADC Architecture for I-UWB Receiver. International Journal of Computer Applications. 57, 15 (November 2012), 32-37. DOI=10.5120/9193-3621

                        @article{ 10.5120/9193-3621,
                        author  = { K. Lokesh Krishna,T. Ramashri },
                        title   = { VLSI Implementation of 4-bit 50Gbps High Speed Pipelined ADC Architecture for I-UWB Receiver },
                        journal = { International Journal of Computer Applications },
                        year    = { 2012 },
                        volume  = { 57 },
                        number  = { 15 },
                        pages   = { 32-37 },
                        doi     = { 10.5120/9193-3621 },
                        publisher = { Foundation of Computer Science (FCS), NY, USA }
                        }
                        %0 Journal Article
                        %D 2012
                        %A K. Lokesh Krishna
                        %A T. Ramashri
                        %T VLSI Implementation of 4-bit 50Gbps High Speed Pipelined ADC Architecture for I-UWB Receiver%T 
                        %J International Journal of Computer Applications
                        %V 57
                        %N 15
                        %P 32-37
                        %R 10.5120/9193-3621
                        %I Foundation of Computer Science (FCS), NY, USA
Abstract

In this work, a 4-bit pipelined ADC that provides the high speed conversion needed in UWB applications with sampling frequency of the order 50 Gbps is proposed. The pipelined ADC designed uses a high speed 1-bit comparator, wide band amplifier, sampling circuit and a high speed buffer. The individual blocks are designed using 130nm CMOS low power library cells. The individual blocks are designed to operate at a frequency greater than 50 Gbps sampling rate. In order to operate increase the operating frequency of the pipelined ADC, Specific new design techniques/algorithms such as power-efficient, capacitor ratio-independent conversion scheme, a pipeline stage-scaling algorithm, a nested CMOS gain-boosting technique, an amplifier and comparator sharing technique, and the use of minimum channel-length, thin oxide transistors with clock bootstrapping and in-line switch techniques are adopted.

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Index Terms
Computer Science
Information Sciences
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Keywords

I-UWB receiver pipelined ADC high speed CMOS gain boosting clock boot strapping

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