Research Article

Impact of CNT’s Diameter Variation on the Performance of CNFET Dual-X CCII

by  Ale Imran, Mohd Azam
journal cover
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 56 - Issue 16
Published: October 2012
Authors: Ale Imran, Mohd Azam
10.5120/8972-3051
PDF

Ale Imran, Mohd Azam . Impact of CNT’s Diameter Variation on the Performance of CNFET Dual-X CCII. International Journal of Computer Applications. 56, 16 (October 2012), 1-6. DOI=10.5120/8972-3051

                        @article{ 10.5120/8972-3051,
                        author  = { Ale Imran,Mohd Azam },
                        title   = { Impact of CNT’s Diameter Variation on the Performance of CNFET Dual-X CCII },
                        journal = { International Journal of Computer Applications },
                        year    = { 2012 },
                        volume  = { 56 },
                        number  = { 16 },
                        pages   = { 1-6 },
                        doi     = { 10.5120/8972-3051 },
                        publisher = { Foundation of Computer Science (FCS), NY, USA }
                        }
                        %0 Journal Article
                        %D 2012
                        %A Ale Imran
                        %A Mohd Azam
                        %T Impact of CNT’s Diameter Variation on the Performance of CNFET Dual-X CCII%T 
                        %J International Journal of Computer Applications
                        %V 56
                        %N 16
                        %P 1-6
                        %R 10.5120/8972-3051
                        %I Foundation of Computer Science (FCS), NY, USA
Abstract

CNFET is generally considered to be one of the most appealing next generation transistors because of its high current carrying capacity and ballistic transport property. This paper investigates the performance analysis of Dual-X Current Conveyor with the CNFET technology, by varying the CNT diameter at 32nm technology node. Current Bandwidth, Input and Output Port resistances of the device along with the average power dissipated are chosen as the parameters of reference for carrying out the analysis. The impact of scaled power supply voltage, on the parameters of interest has also been explored. HSPICE simulator has been used to carry out the extensive simulations at a reduced power supply of ±0. 9V.

References
  • Imran. A, Hasan. M, Islam. A " Optimized design of a 32nmCNFET based low power ultra wide band CCII" accepted for publiication in IEEE Transactions on Nanotechnology.
  • Deng J,Wong HSP" A compact SPICE model for carbon nanotube field effect transistors including non-idealities and application-part1: model of the intrinsic channel region" IEEE Trans Electron Devices; 2007, 54(12); 3186-3194
  • Deng J,Wong HSP" A compact SPICE model for carbon nanotube field effect transistors including non-idealities and application-partII: Full device model and circuit benchmarking" IEEE Trans. Electron Devices; 2007, 54(12): 3195-3205
  • A. Javey, J. Guo, Q. Wang et al ' Self alligned ballistic molecular transistors and electrically parallel nanotube arrays "Nanoletters,4(7), 2004,1319-1322
  • Deng J, Wong HSP, "A circuit compatabile spice model for enhancement mode carbon nanotube field effect transistors" Proc. of the International Conference on simulation of semiconductor process and devices, 2006, 166-169.
  • J. Appenzeller " CarbonNanotubes for high performance electronics (Invited paper), Proceedings of the IEEE 96(2)(2008), 206
  • Patil N,et al "Circuit level performance benchmarking and scalability of carbon nanotube transistor circuits" IEEE Transactions on Nanotechnology,2009;8(1):37-45
  • Patil N, Lin A, Myers ER, Wong HSP "Integrated wafer scale growth and transfer of directional carbon nanotubes and misaligned carbon-nanotube immune logic structures", Proc Symp VLSI techn Digest tech papers, 2008, 205-206.
  • Patil N, Deng J, Lin A ,Wong HSP "Designed methods for misaligned and mispositined carbon nanotube immune circuits", IEEE Trans. Comput Aided Des Integr Syst. 2008, 27(10):1725-1736
  • Patil N, Lin A, Myers E et al "Wafer scale growth and transfer of aligned single wall carbon nanotubes" IEEE Trans. Nanotechnology 2009, 8(4):498-504.
  • Kang S. J, Kocabas C, Ozel T et al "High performance electronics using dense perfectly aligned arrays of single walled carbon nanotube", Nat Nanotechnol. 2007; 2:230-236
  • S. Iijima "Hellical microtubes of graphite ,Nature 354(1991), 56-58
  • Cui Y, Zhong Z, Wang D, Wang WU,Lieber CM" High performance silicon nanowire field effect transistors " Nano letter,2003;3(2):149
  • Zeki. A and Toker. A"The Dual-X CCII –A new active device for tunable continuos time filters",International Journal of Electronics,89,913-923
  • Minaei. S and Yuce. E "A new full wave rectifier circuit employing single dual-x ccii", International Journal of Electronics,Vol95,no8,777-784
  • Sadri Oscan and Hakan Kutman, "A nocel multi input single output filterwith reduced number of passive elements using single current conveyors"IEEE midwest symposium on Circuits and systems,August 2000
  • A. S. Sedra and K. C. Smith "A second generation current conveyor and its applications" IEEE Transaction Circuit Theory,Vol-CT 17, pp 132-134, Feb 1970
  • Semiconductor Industry Association, International Technology roadmap for semiconductors-2005, update:overview and summaries, 2005, online available: http:ww. itrs. net/Links/2005, ITRS/Home 2005htm.
  • D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H. S. P. Wong, "Device scaling limits of Si MOSFETS and their application dependencies", Proc. IEEE, vol. 89, pp. 259-288, Mar 2001.
  • M. S. Dresselhaus, G. Dresselhaus, and P. Avouris, "Carbon Nanotube", Berlin-Germany: Springer-Verlag-2001.
  • P. L. McEuen, M. S. Fuhrer, and P. Hongkun, "Single-walled carbon nanotube electronics", IEEE Trans. Naotechnol. , vol. 1, no. 1, 2002.
  • K. Zhang, U. Bhattacharaya, Z. Chen et al. , "A 3GHz 70 Mb SRAM in 65nm CMOS technology with integrated column base dynamic power supply " IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 146-151, 2006.
  • J. Zhang, N. Patil, and S. Mitra " Design guidelines for metallic-carbon- nanotube tolerant digital logic circuits" in Proc. Des Autom Test Eur, 2008, pp. 1009-1014.
  • N. Patil, A. Lin, J. Zhang, et al. , "Scalable carbon nanotube computational and storage circuits immune to metallic and mispositioned carbon nanotubes, IEEE Trans. Nanotechnol. , vol. 10, no. 4, pp. 744 – 750, 2011.
Index Terms
Computer Science
Information Sciences
No index terms available.
Keywords

Dual-X CCII Carbon Nanotubes Carbon Nanotube field effect transistor Diameter of CNT Inter-CNT Pitch

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