Abstract

Recent advancement in the semiconductor technology allow the hardware engineers to integrate complex modules like processors, peripheral devices, and memory in a single System-on-a-Chip (SoC); where testability, power minimization and management, area minimization are the important system level considerations. Performances both in terms of processing speed and power consumption are becoming more and more challenging in SOC designing. Novel system on chip architectures should be able to execute multiple performances demanding applications while maintaining low power consumption, small area, non-recurring engineering costs and short time to-market. Hence a lot of research is going on to implement CGRA in SOC because Coarse-grained reconfigurable architecture can provide both performance and flexibility. This paper gives a guided tour over a decade of development in CGRA and their significance in SOC design

References

• R. Hartenstein, H. Grünbacher (Editors): The Roadmap to Reconfigurable computing - Proc. FPL2000, Aug. 27-30, 2000; LNCS, Springer-Verlag 2000
• A dynamically reconfigurable system-on-a-chip architecture for future mobile digital signal processing (1999) by Ahmad Alsolaim , Jürgen Becker European signal processing conference
• Reiner W. Hartenstein. Reconfigurable Computing: A New Business Model and its Impact on SoC Design. In Proceedings of DSD'2001. pp. 103~111
• Jurgen Becker, Thilo Pionteck, Christian Habermann, Manfred Glesner "Design and Implementation of a Coarse-Grained Dynamically Reconfigurable Hardware Architecture" Proceeding WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
• Allan Carroll, Stephen Friedman, Brian Van Essen, Aaron Wood, Benjamin Ylvisaker, Carl Ebeling, Scott Hauck, "Designing a Coarse-grained Reconfigurable Architecture for Power Efficiency, Department of Energy NA-22 University Information Technical Interchange Review Meeting, 2007
• K. Compton, Architecture Generation of Customized Reconfigurable Hardware, Ph. D. Thesis, Northwestern University, Dept. of ECE, 2003.
• Carl Ebeling, Darren C. Cronquist, Paul Franklin, Chris Fisher,"RaPiD – A Configurable Computing architecture for Compute Intensive Applications," University of Washington Department of Computer Science & Engineering Tech Report TR-96-11-03.
• K. Eguro, RaPiD-AES: Developing an Encryption-Specific FPGA Architecture, M. S. Thesis, University of Washington, Dept. of EE, 2002.
• H. Singh,M. LeeG. Lu F. Kurdahi, N. Bagherzadeh, "MorphoSys:A Reconfigurable Architecture for Multimedia Applications,"sbcci, pp. 134, XI Brazilian Symposium on Integrated Circuit Design, 1998
• H. Singh, et al, "MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computing-Intensive Applications", IEEE Transaction on Computers, Vol. 49, No. 5, May 2000
• A. Marshall et al. , "A Reconfigurable Arithmetic Array for Multimedia Applications," Proc. ACM/SIGDA FPGA'99, Monterey, Feb. 21-23, 1999
• J. Becker, M. Glesner, A. Alsolaim, J. Starzyk: Fast Communication Mechanisms in Coarse-Grained Dynamically Reconjgurable Array Architectures, Proc. of Second Int'l. Workshop on Engineering of Reconfigurable Hardwareisoftware Objects (ENREGLE'OO, in conjunction with PDPTA 2000), June 23-24, 2000, Las Vegas, USA
• J. Becker, T. Pionteck, M. Glesner: DReAM: A enamically Reconjgurable Architecture for Future Mobile Communication Applications, 10th International Conference on Field Programmable Logic and Applications, Villach, Osterrcich, 2000.
• Jong-eun Lee Kiyoung Cho Nikil D. Dutt"Evaluating Memory Architectures for Media Applications on Coarse-Grained Reconfigurable Architectures. " Proceedings of the Application-Specific Systems, Architectures, and Processors (ASAP'03) 2003 IEEE
• B. Mei, S. Vernalde, D. Verkest, and R. Lauwereins, "Design methodology for tightly coupled VLIW /reconfigurable matrix architecture: a case study," Proc. of Design Automation and Test Conference in Europe, March 2004.
• B. Mei, "A coarse-grained reconfigurable architecture template and its compilation techniques," Ph. D. thesis . Katholieke Universiteit Leuven, Jan. 2005.
• Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man and Rudy Lauwereins: ADRES: An architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix, IMEC, 2003, Kapeldreef 75, B-3001, Leuven, Belgium, DATE 2004
• Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala ," A New Reconfigurable Coarse-Grain Architecture For Multimedia Applications,"Proceedings of the Second NASA/ESAConference on Adaptive Hardware and Systems (AHS 2007), pp 119-126, 2007
• Custom Implementation Of The Coarse-Grained Reconfigurable Adres Architecture For Multimedia Purposes Francisco-Javier Veredas *, Michael Scheppler Field Programmable Logic and Applications, 2005. International Conference on 24-26 Aug. 2005
• Syed Waqar Nabi and Cade C. Wells " A Coarse-Grained Dynamically Reconfigurable Mac Processor For Power-Sensitive Multi-Standard Devices" in Field Programmable Logic and Applications 2008 FPL (2008)
• F. Campii, R. K6nig3, M. Dreschmann3, M. Neukirchner4, D. Picard5, M. Juttner6,E. Schiiler7, A. Deledda2, D. Rossi2, A. Pasinii, M. Hubner3, J. Becker3, R. Guerried " RTL-to-Layout Implementation of an Embedded Coarse Grained Architecture for Dynamically Reconfigurable Computing in Systems-on-Chip" System-on-Chip, 2009. SOC 2009. International Symposium on 5-7 Oct. 2009
• SYSCORE: A Coarse Grained Reconfigurable Array Architecture for Low Energy Biosignal Processing Kunjan Patel, S´eamas McGettrick and Chris J. Bleakley The 19th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines 2011
• C. Liang and X. Huang "SmartCell : A power-efficient reconfigurable architecture for data streaming applications," In Proceedings of IEEE Workshop on Signal Processing Systems (SiPS'08), pp. 257–262, 2008.
• "SmartCell: An Energy Efficient Coarse-Grained Reconfigurable Architecture for Stream-Based Applications" EURASIP Journal on Embedded Systems Volume 2009, Article ID 518659
• Xinming Huang, "SmartCell Architecture, Design and Performance Analysis for Reconfigurable Embedded Computing," In Proceedings of High Performance Embedded Computing Workshop (HPEC), Lexington MA, September 2008
• Dongwook Lee, Manhwee Jo, Kyuseung Han, and Kiyoung Choi, "FloRA: coarse-grained reconfigurable Architecture with floating-point operation capability", 2009 International Conference on Field-Programmable Technology, pp. 376-379, Dec. 2009
• Manhwee Jo, V. K. Prasad Arava, Hoonmo Yang, Kiyoung Choi,"Implementation of floating-point operations for 3D graphics on a coarse-grained reconfigurable architecture", IEEE International SOC Conference, pp. 127-130, Sep. 2007