Research Article
Low Power and Small Area Implementation for OFDM Applications
|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 45 - Issue 9 |
| Published: May 2012 |
| Authors: K. Umapathy, D. Rajaveerappa |
10.5120/6810-9158
|
K. Umapathy, D. Rajaveerappa . Low Power and Small Area Implementation for OFDM Applications. International Journal of Computer Applications. 45, 9 (May 2012), 35-38. DOI=10.5120/6810-9158
@article{ 10.5120/6810-9158,
author = { K. Umapathy,D. Rajaveerappa },
title = { Low Power and Small Area Implementation for OFDM Applications },
journal = { International Journal of Computer Applications },
year = { 2012 },
volume = { 45 },
number = { 9 },
pages = { 35-38 },
doi = { 10.5120/6810-9158 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2012
%A K. Umapathy
%A D. Rajaveerappa
%T Low Power and Small Area Implementation for OFDM Applications%T
%J International Journal of Computer Applications
%V 45
%N 9
%P 35-38
%R 10.5120/6810-9158
%I Foundation of Computer Science (FCS), NY, USA
Abstract
This paper proposes that several FFT algorithms such as radix-2, radix-4 and split radix were designed using VHDL with the multiplication complexity reduced more than 30% by using the newly proposed CSD constant multipliers instead of the programmable multipliers and the simulations of standard 0. 35 ?m. The sizes of FFT/IFFT operations are varied in different applications of OFDM systems. The reorganized Mixed Radix 4-2 Butterfly FFT with bit reversal for the output sequence derived by index decomposition execution is our suggested VLSI system architecture to design the module FFT/IFFT processor for OFDM systems. The output shows that the proposed processor architecture can minimize the area cost while keeping a high-speed processing speed, a decrement of more than 70% of the power consumption/area when compared with complex multiplier
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