Abstract

Vedic multiplier is based on the ancient algorithms (sutras) followed in INDIA for multiplication. This work is based on one of the sutras called "Nikhilam Sutra". These sutras are meant for faster mental calculation. Though faster when implemented in hardware, it consumes more power than the conventional ones. This paper presents a technique to modify the architecture of the Vedic multiplier by using some existing methods in order to reduce power. The 32 X 32 Vedic multiplier is coded in Verilog HDL and Synthesized using Synopsys Design Compiler. The performance is compared in terms of area, data arrival time and power with earlier existing architecture of Vedic multiplier. The proposed design shows very good improvements in terms of power.

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