Research Article
Analysis of Performance factors for PLL based Frequency Synthesizers for Wireless Applications and Impact on Overall Performance
|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 42 - Issue 10 |
| Published: March 2012 |
| Authors: P. Venkateswararao, K. S. Ramesh |
10.5120/5729-7799
|
P. Venkateswararao, K. S. Ramesh . Analysis of Performance factors for PLL based Frequency Synthesizers for Wireless Applications and Impact on Overall Performance. International Journal of Computer Applications. 42, 10 (March 2012), 20-23. DOI=10.5120/5729-7799
@article{ 10.5120/5729-7799,
author = { P. Venkateswararao,K. S. Ramesh },
title = { Analysis of Performance factors for PLL based Frequency Synthesizers for Wireless Applications and Impact on Overall Performance },
journal = { International Journal of Computer Applications },
year = { 2012 },
volume = { 42 },
number = { 10 },
pages = { 20-23 },
doi = { 10.5120/5729-7799 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2012
%A P. Venkateswararao
%A K. S. Ramesh
%T Analysis of Performance factors for PLL based Frequency Synthesizers for Wireless Applications and Impact on Overall Performance%T
%J International Journal of Computer Applications
%V 42
%N 10
%P 20-23
%R 10.5120/5729-7799
%I Foundation of Computer Science (FCS), NY, USA
Abstract
This paper presents the PLL based Frequency Synthesizers, which are used in modern devices for generating wide range of frequencies. The Performance depends on several factors such as phase noise, spurious outputs, loop bandwidth and lock time. The parameters loop bandwidth and lock time are inter-related which are inversely proportional to each other is simulated and the results are given. The Phase Noise for the VCO depends on the frequency range in which it is used and given by Lesson's equation. It varies linearly and L-Band and higher frequencies but varies at 6dB per octave at lower frequencies in hundreds of MHz or tenths of GHz. The results are simulated in MATLAB and presented in this paper.
References
- Shashikant shrimali,Direct Digital Frequency Synthesizer, thesis, Texas Tech University, May 2007
- V. Valenta, G. Baudoin, "Phase Noise Analysis of PLL Based Frequency Synthesizers for Multi-Radio Mobile Terminals", IEEE vol. 50, Issue 2, pp. 429-432, 2010
- Ken Holladay, "Design a PLL for a specific Loop Bandwidth," Fujitsu Microelectronics, Oct 2000
- Curtin,Mike and paul O'Brien,"Phase Locked Loops for high-frequency receivers and transmitters-part 3", Analog Dialogue,33-7,1999
- Banerjee,Dean"PLLPerformance,Simulation and Design" 4th edition Publishing, 2006 stand ISBN – 10: 1598581341.
- D. B. Leeson, "A Simplified model of feedback oscillator noise", IEEE Volume 42, pp. 329-33,Feb 1965
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