Research Article
ASIC Implementation of a High Speed, Low Area Reconfigurable Decimation Filter
|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 34 - Issue 4 |
| Published: November 2011 |
| Authors: Ashish Raman, Vignesh.V, Deepti Kakkar |
10.5120/4089-5898
|
Ashish Raman, Vignesh.V, Deepti Kakkar . ASIC Implementation of a High Speed, Low Area Reconfigurable Decimation Filter. International Journal of Computer Applications. 34, 4 (November 2011), 45-50. DOI=10.5120/4089-5898
@article{ 10.5120/4089-5898,
author = { Ashish Raman,Vignesh.V,Deepti Kakkar },
title = { ASIC Implementation of a High Speed, Low Area Reconfigurable Decimation Filter },
journal = { International Journal of Computer Applications },
year = { 2011 },
volume = { 34 },
number = { 4 },
pages = { 45-50 },
doi = { 10.5120/4089-5898 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2011
%A Ashish Raman
%A Vignesh.V
%A Deepti Kakkar
%T ASIC Implementation of a High Speed, Low Area Reconfigurable Decimation Filter%T
%J International Journal of Computer Applications
%V 34
%N 4
%P 45-50
%R 10.5120/4089-5898
%I Foundation of Computer Science (FCS), NY, USA
Abstract
Decimation filter is used to reduce the sampling rate for succeeding stages of an oversampling ADC. The speed of a successive-approximation ADC predominately depends on the decimator speed. This necessitates a need to design a high speed decimation filter to improve the overall system performance. A reconfigurable architecture is applied for the design of decimator to serve this purpose. Results show that delay of a Reconfigurable Decimator is reduced by 29.74% compared to a Normal Decimation filter. The Number of Slices and 4 Input LUTs are reduced by 6% and 7% each, which reduces the Area.
References
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