International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
Volume 30 - Issue 4 |
Published: September 2011 |
Authors: Gautam A. Shah, Tejmal S. Rathore |
![]() |
Gautam A. Shah, Tejmal S. Rathore . An Analog Architecture for Split-Radix DHT. International Journal of Computer Applications. 30, 4 (September 2011), 24-31. DOI=10.5120/3630-5069
@article{ 10.5120/3630-5069, author = { Gautam A. Shah,Tejmal S. Rathore }, title = { An Analog Architecture for Split-Radix DHT }, journal = { International Journal of Computer Applications }, year = { 2011 }, volume = { 30 }, number = { 4 }, pages = { 24-31 }, doi = { 10.5120/3630-5069 }, publisher = { Foundation of Computer Science (FCS), NY, USA } }
%0 Journal Article %D 2011 %A Gautam A. Shah %A Tejmal S. Rathore %T An Analog Architecture for Split-Radix DHT%T %J International Journal of Computer Applications %V 30 %N 4 %P 24-31 %R 10.5120/3630-5069 %I Foundation of Computer Science (FCS), NY, USA
The fast Hartley transform and algorithm for DHT was introduced by Bracewell. The split radix decimation-in-frequency algorithm that requires less number of operation counts as compared to the radix-2 and radix-4 algorithms was developed by Sorenson et al. In this paper, an analog architecture for a split radix decimation-in-time algorithm is proposed. It utilizes three different structures in the signal flow diagram. It exhibits a recursive pattern and is modular. The validity of the analog architecture is tested by simulating it with the help of the Orcad PSpice.