Research Article
Article:Improved Carry Select Adder with Reduced Area and Low Power Consumption
|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 3 - Issue 4 |
| Published: June 2010 |
| Authors: Padma Devi, Ashima Girdher, Balwinder Singh |
10.5120/723-1016
|
Padma Devi, Ashima Girdher, Balwinder Singh . Article:Improved Carry Select Adder with Reduced Area and Low Power Consumption. International Journal of Computer Applications. 3, 4 (June 2010), 14-18. DOI=10.5120/723-1016
@article{ 10.5120/723-1016,
author = { Padma Devi,Ashima Girdher,Balwinder Singh },
title = { Article:Improved Carry Select Adder with Reduced Area and Low Power Consumption },
journal = { International Journal of Computer Applications },
year = { 2010 },
volume = { 3 },
number = { 4 },
pages = { 14-18 },
doi = { 10.5120/723-1016 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2010
%A Padma Devi
%A Ashima Girdher
%A Balwinder Singh
%T Article:Improved Carry Select Adder with Reduced Area and Low Power Consumption%T
%J International Journal of Computer Applications
%V 3
%N 4
%P 14-18
%R 10.5120/723-1016
%I Foundation of Computer Science (FCS), NY, USA
Abstract
Power dissipation is one of the most important design objectives in integrated circuits, after speed. As adders are the most widely used components in such circuits, design of efficient adder is of much concern for researchers. This paper presents performance analysis of different Fast Adders. The comparison is done on the basis of three performance parameters i.e. Area, Speed and Power consumption. We present a modified carry select adder designed in different stages. Results obtained from modified carry select adders are better in area and power consumption.
References
Index Terms
Keywords