Research Article
VHDL Implementation of GCD Processor with Built in Self Test Feature
|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 25 - Issue 2 |
| Published: July 2011 |
| Authors: Rekha Devi, Jaget Singh, Mandeep Singh |
10.5120/3000-4034
|
Rekha Devi, Jaget Singh, Mandeep Singh . VHDL Implementation of GCD Processor with Built in Self Test Feature. International Journal of Computer Applications. 25, 2 (July 2011), 50-54. DOI=10.5120/3000-4034
@article{ 10.5120/3000-4034,
author = { Rekha Devi,Jaget Singh,Mandeep Singh },
title = { VHDL Implementation of GCD Processor with Built in Self Test Feature },
journal = { International Journal of Computer Applications },
year = { 2011 },
volume = { 25 },
number = { 2 },
pages = { 50-54 },
doi = { 10.5120/3000-4034 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2011
%A Rekha Devi
%A Jaget Singh
%A Mandeep Singh
%T VHDL Implementation of GCD Processor with Built in Self Test Feature%T
%J International Journal of Computer Applications
%V 25
%N 2
%P 50-54
%R 10.5120/3000-4034
%I Foundation of Computer Science (FCS), NY, USA
Abstract
The Very Large Scale Integration (VLSI) has a dramatic impact on the growth of digital technology. VLSI has not only reduced the size and the cost, but also increased the complexity of the circuits. Due increase there is a problem of circuit testing, which becomes increasingly difficult as the scale of integration grows. One solution to this problem is to add logic to the IC so that it can test itself. In this paper we have design GCD (greatest common divider) processors in VHDL with BIST capability and compared the area overhead of with and without BIST.
References
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