Research Article
Low Power, Low Area and High Performance Hybrid Type Dynamic CAM Design
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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| Volume 22 - Issue 6 |
| Published: May 2011 |
| Authors: Nagarjuna.V, Harish M Kittur |
10.5120/2585-3571
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Nagarjuna.V, Harish M Kittur . Low Power, Low Area and High Performance Hybrid Type Dynamic CAM Design. International Journal of Computer Applications. 22, 6 (May 2011), 39-43. DOI=10.5120/2585-3571
@article{ 10.5120/2585-3571,
author = { Nagarjuna.V,Harish M Kittur },
title = { Low Power, Low Area and High Performance Hybrid Type Dynamic CAM Design },
journal = { International Journal of Computer Applications },
year = { 2011 },
volume = { 22 },
number = { 6 },
pages = { 39-43 },
doi = { 10.5120/2585-3571 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2011
%A Nagarjuna.V
%A Harish M Kittur
%T Low Power, Low Area and High Performance Hybrid Type Dynamic CAM Design%T
%J International Journal of Computer Applications
%V 22
%N 6
%P 39-43
%R 10.5120/2585-3571
%I Foundation of Computer Science (FCS), NY, USA
Abstract
Content-addressable memories (CAMs) are hardware search engines that are much faster than algorithmic approaches for search-intensive applications. CAMs are composed of conventional semiconductor memory (usually SRAM) with added comparison circuitry that enables a search operation to complete in a single clock cycle. In case of advanced applications we need large sized CAM but it has the disadvantage of high power consumption. To overcome the drawbacks we need to reduce the power consumption of the CAM when we search the data. This paper proposes an idea for improving power, area and performance of the system of recently proposed high Performance Hybrid-Type CAM Designs. For this we replace the basic 9T CAM cell with a 4T CAM cell. The simulation results show the success of the method.
References
- K. Pagiamtzis and A. Sheikholeslami, “Content-addressable memory(CAM) circuits and architectures: A tutorial and survey,” IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 712–727, Mar. 2006.
- Content Addressable Memory for Low Power and High Performance Applications by Ataur R. Patwary, Bibiche M. Geuskens, Shih-Lien L. Lu, Solid-State Circuits, no.8, April 2008.
- An Improved Comparison Circuit for Low Power Pre-computation-Based Content-Addressable Memory designs by Yu-Ting Pai, Chia-Han Lee, and Shanq-Jang Ruan, IEEE. Solid-State Circuits, vol. 97,no. 9, June. 2009.
- Design of Low-Power Content Addressable Memory Cell by KUO-HSING CHENG, CHIA-HUNG WEI, JIANN-CHYI RAU, Solid-State Circuits.
- H.Miyatake, M.Tanaka and Y.Mori,” A Design for high speed low power CMOS fully parallel Content Addressable Memory macros”, IEEE J.Solid-StateCircuits,vol.38,no.11,pp.1958–1966, Nov 2003.
- C.A.ZukowskiandS.Y.Wang,” Use of selective precharge for low power content addressable memories”, in Proc.Int.Symp.Circuits and Syst.,1997,pp.1788–1791.
- Yen-Jen Chang and Yuan –Hong Liao,”Hybrid-Type CAM design for both power and performance efficiency”, in VLSI systems, Vol 16,No:8,Aug 2008.
- Jose G.Delgado –Frias, Andy Yu and Jabulani Nyathi, “A Dynamic Content Addressable Memory Cell”, in VLSI Synstems, Vol 99, No:1, Sep 1999.
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