Research Article

FPGA Implementation of RSA Encryption System

by  Sushanta Kumar Sahu, Manoranjan Pradhan
journal cover
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 19 - Issue 9
Published: April 2011
Authors: Sushanta Kumar Sahu, Manoranjan Pradhan
10.5120/2391-3173
PDF

Sushanta Kumar Sahu, Manoranjan Pradhan . FPGA Implementation of RSA Encryption System. International Journal of Computer Applications. 19, 9 (April 2011), 10-12. DOI=10.5120/2391-3173

                        @article{ 10.5120/2391-3173,
                        author  = { Sushanta Kumar Sahu,Manoranjan Pradhan },
                        title   = { FPGA Implementation of RSA Encryption System },
                        journal = { International Journal of Computer Applications },
                        year    = { 2011 },
                        volume  = { 19 },
                        number  = { 9 },
                        pages   = { 10-12 },
                        doi     = { 10.5120/2391-3173 },
                        publisher = { Foundation of Computer Science (FCS), NY, USA }
                        }
                        %0 Journal Article
                        %D 2011
                        %A Sushanta Kumar Sahu
                        %A Manoranjan Pradhan
                        %T FPGA Implementation of RSA Encryption System%T 
                        %J International Journal of Computer Applications
                        %V 19
                        %N 9
                        %P 10-12
                        %R 10.5120/2391-3173
                        %I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper presents the architecture and modeling of RSA public key encryption/decryption systems. It supports multiple key sizes like 128 bits, 256 bits, 512 bits. Therefore it can easily be fit into the different systems requiring different levels of security. In this paper simple shift and add algorithm is used to implement the blocks. It makes the processing time faster and used comparatively smaller amount of space in the FPGA due to its reusability. Each block is coded with Very High Speed Integrated Circuit Hardware Description Language. The VHDL code is synthesized and simulated using Xilinx-ISE 10.1. It is verified that this architecture support multiple key of 128bits, 256bits, and 512 bits

References
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Index Terms
Computer Science
Information Sciences
No index terms available.
Keywords

RSA VHDL FPGA modular multiplication.

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