Abstract

Simultaneous Localization and Mapping (SLAM) is critical for autonomous systems because it enables real-time environmental mapping and navigation. Implementing SLAM algorithms in hardware, particularly on low-resource platforms, poses challenges owing to the computational complexity of operations such as matrix multiplications and quaternion transformations. This study introduces a novel accelerated core for SLAM algorithms that is optimized for hardware resource efficiency and high computational performance. By leveraging dedicated instruction set and memory reuse strategies, this core supports various SLAM approaches. The experimental results demonstrate the coprocessor's high precision, low resource consumption, and adaptability to multiple SLAM algorithms.

References

• Q. Liu, Z. Wan, B. Yu, W. Liu, S. Liu, and A. Raychowdhury, “An energy-efficient and runtime-reconfigurable FPGA-based accelerator for robotic localization systems,” in Proc. IEEE Custom Integr. Circuits Conf. (CICC), 2022, pp. 1–2.
• Y. Gan et al., "Eudoxus: Characterizing and Accelerating Localization in Autonomous Machines," HPCA, Mar. 2021.
• J. Wang et al., “A Reconfigurable matrix multiplication coprocessor with high area and energy efficiency for visual intelligent and autonomous mobile robots,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), 2021, pp. 1–3, doi: 10.1109/A-SSCC53895.2021.9634793.
• N. Cao, M. Chang, and A. Raychowdhury, “A 65-nm 8-to-3-b 1.0–0.36-V 9.1–1.1-TOPS/W hybrid-digital-mixed-signal computing platform for accelerating swarm robotics,” IEEE J. Solid-State Circuits, vol. 55, no. 1, pp. 49–59, Jan. 2020, doi: 10.1109/JSSC.2019.2935533.
• Q. Liu et al., "π-BA: Bundle Adjustment Hardware Accelerator Based on Distribution of 3D-Point Observations," TC, July 2020.
• Z. Li et al., "An 879GOPS 243mw 80fps VGA Fully Visual CNNSLAM Processor for Wide-Range Autonomous Exploration," ISSCC, Feb. 2019.
• A. Suleiman et al., "Navion: A 2-mw Fully Integrated Real-Time Visual-Inertial Odometry Accelerator for Autonomous Navigation of Nano Drones," JSSC, Apr. 2019.
• Y. Kim, D. Shin, J. Lee, Y. Lee, and H.-J. Yoo, “A 0.55 V 1.1 mW artificial intelligence processor with on-chip PVT compensation for autonomous mobile robots,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 65, no. 2, pp. 567–580, Feb. 2018.
• J. E. Volder, “The CORDIC trigonometric computing technique,” IRE Trans. Electron. Comput., vol. EC-8, no. 3, pp. 330–334, Sep. 1959, doi: 10.1109/TEC.1959.5222693.
• M. Gautschi, M. Schaffner, F. K. Gürkaynak, and L. Benini, “An extended shared logarithmic unit for nonlinear function Kernel acceleration in a 65-nm CMOS multicore cluster,” IEEE J. Solid-State Circuits, vol. 52, no. 1, pp. 98–112, Jan. 2017, doi: 10.1109/JSSC.2016.2626272.
• D. T. Tertei, J. Piat, and M. Devy, “FPGA design of EKF block accelerator for 3D visual SLAM,” Comput. Elect. Eng., vol. 55, pp. 123–137, Oct. 2016.
• Shivaprasad B K, K. D. Shinde, and V. Muddi, “Design and implementation of parallel floating point matrix multiplier for quaternion computation,” in Proc. Int. Conf. Control Instrument. Commun. Comput. Technol. (ICCICCT), 2015, pp. 289–293, doi: 10.1109/ICCICCT.2015.7475292.
• E. Doukhnitch and E. Ozen, “Hardware-oriented algorithm for quaternion-valued matrix decomposition,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, no. 4, pp. 225–229, Apr. 2011, doi: 10.1109/TCSII.2011.2111590.
• G. Rubin, M. Omieljanowicz, and A. Petrovsky, “Reconfigurable FPGA-based hardware accelerator for embedded DSP,” in Proc. 14th Int. Conf. Mixed Design Integer. Circuits Syst., 2007, pp. 147–151, doi: 10.1109/MIXDES.2007.4286138.