International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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Volume 186 - Issue 62 |
Published: January 2025 |
Authors: Aravalli Sainath Chaithanya, Myadari Radhika |
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Aravalli Sainath Chaithanya, Myadari Radhika . Design and Functional Verification of a 1x4 Switch for Packet-Based Data Transmission. International Journal of Computer Applications. 186, 62 (January 2025), 1-10. DOI=10.5120/ijca2025924434
@article{ 10.5120/ijca2025924434, author = { Aravalli Sainath Chaithanya,Myadari Radhika }, title = { Design and Functional Verification of a 1x4 Switch for Packet-Based Data Transmission }, journal = { International Journal of Computer Applications }, year = { 2025 }, volume = { 186 }, number = { 62 }, pages = { 1-10 }, doi = { 10.5120/ijca2025924434 }, publisher = { Foundation of Computer Science (FCS), NY, USA } }
%0 Journal Article %D 2025 %A Aravalli Sainath Chaithanya %A Myadari Radhika %T Design and Functional Verification of a 1x4 Switch for Packet-Based Data Transmission%T %J International Journal of Computer Applications %V 186 %N 62 %P 1-10 %R 10.5120/ijca2025924434 %I Foundation of Computer Science (FCS), NY, USA
This work presents the design and functional verification of a 1x4 switch, a key component in packet-based communication protocols operating at the network layer of the TCP/IP model. The switch facilitates intelligent routing of data packets from a single input to multiple outputs, ensuring efficient and reliable communication. Addressing the growing need for robust verification in modern ASIC design—where verification consumes 60% of the design cycle and 90% of chip failures result from inadequate verification—this study develops a System Verilog-based verification environment. The design incorporates finite state machines (FSMs), FIFOs, and memory modules, with extensive simulation across diverse scenarios to validate functionality. State-of-the-art EDA tools, including Xilinx ISE 14.7 and Synopsys VCS 2021.09, are utilized for design synthesis and verification. This approach achieves comprehensive coverage, enhances reliability, and ensures reusability, making it a significant contribution to the field of network hardware design.