Research Article

Design and Functional Verification of a 1x4 Switch for Packet-Based Data Transmission

by  Aravalli Sainath Chaithanya, Myadari Radhika
journal cover
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 186 - Issue 62
Published: January 2025
Authors: Aravalli Sainath Chaithanya, Myadari Radhika
10.5120/ijca2025924434
PDF

Aravalli Sainath Chaithanya, Myadari Radhika . Design and Functional Verification of a 1x4 Switch for Packet-Based Data Transmission. International Journal of Computer Applications. 186, 62 (January 2025), 1-10. DOI=10.5120/ijca2025924434

                        @article{ 10.5120/ijca2025924434,
                        author  = { Aravalli Sainath Chaithanya,Myadari Radhika },
                        title   = { Design and Functional Verification of a 1x4 Switch for Packet-Based Data Transmission },
                        journal = { International Journal of Computer Applications },
                        year    = { 2025 },
                        volume  = { 186 },
                        number  = { 62 },
                        pages   = { 1-10 },
                        doi     = { 10.5120/ijca2025924434 },
                        publisher = { Foundation of Computer Science (FCS), NY, USA }
                        }
                        %0 Journal Article
                        %D 2025
                        %A Aravalli Sainath Chaithanya
                        %A Myadari Radhika
                        %T Design and Functional Verification of a 1x4 Switch for Packet-Based Data Transmission%T 
                        %J International Journal of Computer Applications
                        %V 186
                        %N 62
                        %P 1-10
                        %R 10.5120/ijca2025924434
                        %I Foundation of Computer Science (FCS), NY, USA
Abstract

This work presents the design and functional verification of a 1x4 switch, a key component in packet-based communication protocols operating at the network layer of the TCP/IP model. The switch facilitates intelligent routing of data packets from a single input to multiple outputs, ensuring efficient and reliable communication. Addressing the growing need for robust verification in modern ASIC design—where verification consumes 60% of the design cycle and 90% of chip failures result from inadequate verification—this study develops a System Verilog-based verification environment. The design incorporates finite state machines (FSMs), FIFOs, and memory modules, with extensive simulation across diverse scenarios to validate functionality. State-of-the-art EDA tools, including Xilinx ISE 14.7 and Synopsys VCS 2021.09, are utilized for design synthesis and verification. This approach achieves comprehensive coverage, enhances reliability, and ensures reusability, making it a significant contribution to the field of network hardware design.

References
  • Balchunas, ”Hubs vs. Switches vs. Routers v1.33,” 2014. [Online]. Available: https://www.routeralley.com/ guides/hubs_switches_routers.pdf. [Accessed: Dec. 11, 2024].
  • M. A. Javed Sethi, F. A. Hussin, and N. H. Hamid, ”Review of Network on Chip Architectures,” Recent Advances in Electrical & Electronic Engineering, vol. 10, pp. 4-29, 2017. doi: 10.2174/2352096510666170425102503.
  • K. Golshan, ASIC Design Implementation Process: A Complete Framework, 1st ed., Springer Cham, 2024. doi: 10.1007/978-3-031-58653-8.
  • C. Spear, SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Springer Science+Business Media, 2006. ISBN-13: 978-0387270364, e-ISBN-13: 978- 0387270388. Available: Springer Link.
  • Y. Gao, ”Research and analysis of FIFO related working principles,” Proc. 5th Int. Conf. Computing and Data Science, 2023. doi: 10.54254/2755-2721/14/20230770.
  • E. Lavanya, K. Sharath Chandra, K. Naveen, and K. Rupesh, ”Router 1x3-RTL router design and verification,” Int. Res. J. Modernization Eng. Technol. Sci., vol. 4, no. 5, May 2022. [Online]. Available: https://www.irjmets.com.
  • P. Musale, P. Thakre, and Y. Raut, ”Design and verification of 1*3 router,” Int. J. Modern Trends Sci. Technol., vol. 9, no. 6, pp. 184-194, 2023. doi: 10.46501/IJMTST0906027.
  • Dr. Uma B. V and R. Pakala, ”Design and implementation of four-port router for network on chip,” Int. J. Eng. Res. Technol., vol. 8, no. 6, pp. 520-524, June 2019. [Online]. Available: Publisher Link.
  • J. Jose and M. T. V, ”Design and verification of an efficient packet-based switching network-on-chip,” Int. J. Sci. Res. Eng. Manag., vol. 6, no. 7, pp. 1, Jul. 2022. doi: 10.55041/IJSREM15285.
  • A. S. Chaithanya, D. Sindhuja, D. Bhavana, and P. Vennela, ”Design and interfacing of I2C master with register and LCD slaves,” Int. J. Eng. Adv. Technol. (IJEAT), vol. 9, no. 4, pp. 2355–2360, Apr. 2020. doi: 10.35940/ijeat.D7901.049420.
  • S. Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, 2nd ed., Prentice Hall PTR, 2003. ISBN: 0-13- 044911-3. Available: Pearson Link.
  • ”SystemVerilog Simple Testbench,” ChipVerify. [Online]. Available: https://www.chipverify.com/ systemverilog/systemverilog-simple-testbench.
  • A. Sainath Chaithanya, S. Sulthana, B. Yamuna, and C. Haritha, ”Design of AMBA AXI4-Lite for effective read/write transactions with a customized memory,” Int. J. Emerg. Technol., vol. 11, Issue.1, pp. 396–402, 2020. Available: Publisher Link.
  • P. Jain and S. Rao, ”Design and Verification of Advanced Microcontroller Bus Architecture-Advanced Peripheral Bus (AMBA-APB) Protocol,” 2021 Third International Conference on Intelligent Communication Technologies and Virtual Mobile Networks (ICICV), Tirunelveli, India, 2021, pp. 462- 467. doi: 10.1109/ICICV50876.2021.9388549.
Index Terms
Computer Science
Information Sciences
Data Packet
Functional Verification
Routers
Switch
VLSI-SoC
Keywords

1x4 Switch Finite State Machine (FSM) FIFO Functional Verification Packet-Based Communication and System Verilog

Powered by PhDFocusTM