Abstract

Advanced Encryption Standard (AES) is one of the most popular encryption algorithms. The algorithm uses a combination of Exclusive-OR operations (XOR), octet substitution with an S-box, row and column rotations, and a Mix Column. In this paper the parallel implementation of AES cryptography algorithm is evaluated and compared in terms of running time, speed up and parallel efficiency. The parallel implementation of AES is implemented using message passing interface (MPI) library, and the results have been conducted using IMAN1 Supercomputer. The experimental results show that the run time of AES algorithm is decreased as the number of processors is increased. Moreover, the speedup for the data size of 16, 32, 64, 128, 256, and 1024-KB is increased when the number of processors is equal to 2, 4, 8, and 16.

References

• Joan Daemen, Vincent Rijmen, The Design of Rijndael: AES – The Advanced Encryption Standard, Springer, 2002. ISBN 3-540-42580-2.
• Le, D., Chang, J., Gou, X., Zhang, A. and Lu, C., 2010, April. Parallel AES algorithm for fast data encryption on GPU. In Computer Engineering and Technology (ICCET), 2010 2nd International Conference on (Vol. 6, pp. V6-1). IEEE.
• Di Natale, G., Doulcier, M., Flottes, M.L. and Rouzeyre, B., 2009. A reliable architecture for parallel implementations of the advanced encryption standard. Journal of Electronic Testing, 25(4-5), pp.269-278.
• Maha Saadeh, Huda Saadeh, and Mohammad Qatawneh. Performance Evaluation of Parallel Sorting Algorithms on IMAN1 Supercomputer, International Journal of Advanced Science and Technology, 95, 2016, pp. 57-72.
• Qatawneh Mohammed. Embedding Linear Array Network into the tree-hypercube Network, European Journal of Scientific Research, 10(2). 2005, pp. 72-76.
• Mohammad Qatawneh, Ahmad Alamoush, Ja'far Alqatawna. Section Based Hex-Cell Routing Algorithm (SBHCR), International Journal of Computer Networks & Communications (IJCNC), 7(1). 2015.
• Mohammad Qatawneh. Multilayer Hex-Cells: A New Class of Hex-Cell Interconnection Networks for Massively Parallel Systems, International journal of Communications, Network and System Sciences, 4(11). 2011.
• Mohammad Qatawneh. Embedding Binary Tree and Bus into Hex-Cell Interconnection Network, Journal of American Science, 7(12). 2011.
• Qatawneh Mohammad, Hebatallah Khattab. New Routing Algorithm for Hex-Cell Network, International Journal of Future Generation Communication and Networking, 8(2). 2015.
• Mohammad Qatawneh. New Efficient Algorithm for Mapping Linear Array into Hex-Cell Network, International Journal of Advanced Science and Technology, 90, 2016.
• S.K. Mathew, et al. 53 Gbps Native GF (24)2 Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors, JSSC, vol.46, no.4, p.767-776, April (2011).
• J. Ortega, et al. Parallelizing AES on multicores and GPUs, Electro/Information Technology (EIT), 2011 IEEE International Conference on, May (2011).
• M. Kumar and A. Singhal. Efficient implementation of Advanced Encryption Standard (AES) for ARM based platforms, Recent Advances in Information Technology, 2012 1st International Conference on, March (2012).
• Quinn, M.J. and Quinn, M.J., 1994. Parallel computing: theory and practice (Vol. 2). New York: McGraw-Hill.