Abstract

Static Random Access Memory (SRAM) is a volatile memory that is widely used in every embedded system – Silicon on Chip (SoC), Digital Signal Processing (DSP), Microcontroller, Field Programmable Gate Array (FPGA) and Video applications. It is also used in register, cache and cache-less applications due to large storage *density, reduced read-write access time, low power consumption and stability. Thus, this paper presents the design principle of SRAM at the 45nm technology node, the peripheral building blocks and functionalities, operations, transistor scalene challenges, and process variation effects of SRAM designs. A clear detail schematic diagrams using Cadence Virtuoso design tool for IC design was used for designing the peripheral circuitry and the SRAM cell.

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