Research Article
Design and Implementation of 8 point FFT using Verilog HDL
|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 177 - Issue 11 |
| Published: Oct 2019 |
| Authors: Sonali Kangralkar, Rajashri Khanai |
10.5120/ijca2019919440
|
Sonali Kangralkar, Rajashri Khanai . Design and Implementation of 8 point FFT using Verilog HDL. International Journal of Computer Applications. 177, 11 (Oct 2019), 4-6. DOI=10.5120/ijca2019919440
@article{ 10.5120/ijca2019919440,
author = { Sonali Kangralkar,Rajashri Khanai },
title = { Design and Implementation of 8 point FFT using Verilog HDL },
journal = { International Journal of Computer Applications },
year = { 2019 },
volume = { 177 },
number = { 11 },
pages = { 4-6 },
doi = { 10.5120/ijca2019919440 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2019
%A Sonali Kangralkar
%A Rajashri Khanai
%T Design and Implementation of 8 point FFT using Verilog HDL%T
%J International Journal of Computer Applications
%V 177
%N 11
%P 4-6
%R 10.5120/ijca2019919440
%I Foundation of Computer Science (FCS), NY, USA
Abstract
The importance of Digital Signal Processing (DSP) algorithms have increased drastically in recent times, the two important techniques of DSP are the Discrete Fourier Transform(DFT) and the Fast Fourier Transform(FFT). DFT is broadly used in the applications such as convolution, linear filtering etc. Another algorithm to compute DFT efficiently is the Fast Fourier Transform (FFT). Fast Fourier Transform processor has an important role in the field of communication system such as audio broadcasting and digital video etc. This paper deals with the designing of an 8 point FFT using radix-2 DIT FFT algorithm. This 8 point FFT design is implemented using Verilog HDL in Xilinx ISE Software.
References
- Arunkumar P. Chavan, Sowmya Nag K., “VLSI Implementation of Split-Radix FFT for High Speed Applications”International Journal of Computer Applications, January 2017
- Muniandi Kannan and Srinivasa Srivatsa,”Hardware Implementation Low Power High Speed FFT Core” The International arab journal of Information Technology, Vol.6,, January 2009
- Marimuthu R* and P.S Mallick, “Design of Efficient Signed Multiplier Using Compressors for FFT Architecture” Journal of Engineering Science and Technology Review, May 2017
- K.Baboji, Sriadibhatla.Sridevi, “FFT Implementation Using Floating Point Fused Multiplier with Four Term Adder” Dept. of Micro and Nano Electronics School of Electronics Engineering VIT University
- Lamessa Dingeta, Gelaye Geresu, “Design of Pipelined Butterflies from Radix-2 FFT with Decimation in Time Algorithm using Efficient Adder Compressors” International Journal of VLSI System Design and Communiation Systems, December 2016.
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